参数资料
| 型号： | ISL6322IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 25/41页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6322
controller latches off and PGOOD will not return high until
OUTPUT PRECHARGED
ABOVE DAC LEVEL
after a successful soft-start. In the case of an undervoltage
event, PGOOD will return high when the output voltage
returns to within the undervoltage.
OUTPUT PRECHARGED
BELOW DAC LEVEL
-
OCL
+
170 μ A
I 1
GND>
V OUT (0.5V/DIV)
I 2 C OVP
VDAC
REPEAT FOR
EACH CHANNEL
GND>
T1 T2
T3
EN (5V/DIV)
REGISTER
VRSEL
+175mV,
+250mV,
+350mV
-
OCP
+
125 μ A
I AVG
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6322-BASED
MULTIPHASE CONVERTER
Pre-Biased Soft-Start
The ISL6322 also has the ability to start up into a
V OVP
SOFT-START, FAULT
AND CONTROL LOGIC
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
VSEN
RGND
+
-
x1
-
+
-
+
OV
UV
PGOOD
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
VDIFF
0.60 x DAC
ISL6322 INTERNAL CIRCUITRY
abrupt correction in the output voltage down to the DAC-set
level.
Fault Monitoring and Protection
The ISL6322 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6322 is regulating the
output voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied to a +5V source
through a resistor.
During shutdown and soft-start PGOOD pulls low and
releases high after a successful soft-start and the output
voltage is operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected or when the controller is disabled by a reset from
EN, EN_PH4, POR, or one of the no-CPU VID codes. In the
event of an overvoltage or overcurrent condition, the
25
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 70% of the VID code.
Overvoltage Protection
The ISL6322 constantly monitors the sensed output voltage
on the VDIFF pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level
actions are taken by the ISL6322 to protect the
microprocessor load. The overvoltage protection trip level
changes depending on what mode of operation the controller
is in and what state the I 2 C registers and the VRSEL pin are
in. Table 6 and 7 below list what the OVP trip levels are under
all conditions (see pages 27 through 31 for details of
controlling OVP thresholds with I 2 C).
At the inception of an overvoltage event, LGATE1, LGATE2
and LGATE3 are commanded high, PWM4 is commanded
low, and the PGOOD signal is driven low. This turns on the
all of the lower MOSFETs and pulls the output voltage below
FN6328.2
August 2, 2007
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