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参数资料
| 型号： | ISL6323EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 22/36页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL6323 |
| 标准包装： | 1 |
| 系列： | * |
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ISL6323
the channel firing order and timing for 2-phase operation
(see “PWM Operation” on page 13 for details). If Channel 4
and/or Channel 3 are disabled, then the corresponding
.
PWMn and ISENn+ pins may be left unconnected.
Soft-Start Output Voltage Targets
Once the POR and Phase Detect blocks and enable
comparator are satisfied, the controller will begin the
V NB
400mV/DIV
V CORE
400mV/DIV
soft-start sequence and will ramp the CORE and NB output
voltages up to the SVI interface designated target level if the
controller is set SVI mode. If set to PVI mode, the North
Bridge regulator is disabled and the core is soft started to the
level designated by the parallel VID code.
EN
5V/DIV
TDA
TDB
VDDPWRGD
5V/DIV
SVI MODE
Prior to soft-starting both CORE and NB outputs, the
ISL6323 must check the state of the SVI interface inputs to
determine the correct target voltages for both outputs. When
the controller is enabled, the state of the VFIXEN, SVD and
SVC inputs are checked and the target output voltages set
for both CORE and NB outputs are set by the DAC (see
only change if the EN signal is pulled low or after a POR
reset of VCC.
Soft-Start
The soft-start sequence is composed of three periods, as
shown in Figure 13. At the beginning of soft-start, the DAC
immediately obtains the output voltage targets for both
outputs by decoding the state of the SVI or PVI inputs. A
100μs fixed delay time, TDA, proceeds the output voltage
rise. After this delay period the ISL6323 will begin ramping
both CORE and NB output voltages to the programmed DAC
level at a fixed rate of 3.25mV/μs. The amount of time
required to ramp the output voltage to the final DAC voltage
is referred to as TDB, and can be calculated as shown in
Equation 19.
100μs/DIV
FIGURE 13. SOFT-START WAVEFORMS
Pre-Biased Soft-Start
The ISL6323 also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
the DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
in the output voltage down to the DAC-set level.
Both CORE and NB output support start up into a
pre-charged output.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
V DAC
TDB = ------------------------------
3.25 × 10
– 3
After the DAC voltage reaches the final VID setting,
VDDPWRGD will be set to high.
(EQ. 19)
OUTPUT PRECHARGED
BELOW DAC LEVEL
V CORE
400mV/DIV
EN
5V/DIV
100μs/DIV
FIGURE 14. SOFT-START WAVEFORMS FOR ISL6323-BASED
MULTIPHASE CONVERTER
22
FN9278.5
May 17, 2011
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| ISL6323IRZ-T | 功能描述:IC HYBRID CTRLR PWM MONO 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE+NORTHBRIDGE, PROG PSI, 3.4MHZ SVI - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324ACRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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