参数资料
型号: ISL6323EVAL1Z
厂商: Intersil
文件页数: 27/36页
文件大小: 0K
描述: EVAL BOARD 1 FOR ISL6323
标准包装: 1
系列: *
ISL6323
PVCC
BOOT
C GD
D
and Core regulators, it is important to set the R SET value
and the inductor RC filter gain, K, properly. See “Continuous
Balance” on page 15 for more details on the application of
R HI1
R LO1
UGATE
G
R G1
R GI1
C GS
C DS
Q1
the R SET resistor and the RC filter gain.
There are 3 separate cases to consider when calculating
these component values. If the system under design will
never utilize the North Bridge regulator and the ISL6323 will
S
PHASE
FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
always be in parallel mode, then follow the instructions for
Case 3 and only calculate values for Core regulator
components.
For all three cases, use the expected VID voltage that would
PVCC
C GD
D
be used at TDC for Core and North Bridge for the V CORE
and V NB variables, respectively.
CASE 1
I Core
? DCR NB < -------------------------- ? DCR Core
R HI2
R LO2
LGATE
G
R G2
R GI2
C DS
I NB
MAX
MAX
N
(EQ. 31)
C GS
S
Q2
In Case 1, the DC voltage across the North Bridge inductor
at full load is less than the DC voltage across a single phase
of the Core regulator while at full load. Here, the DC voltage
across the Core inductors must be scaled down to match the
R 1
DCR NB ? C NB
400 DCR NB ? K ? V IN – V NB V NB ?
2 ? L NB ? f S V IN ?
R SET = ---------- ? ------------------------------ ? ? I OCP + ----------------------------- ? ----------- ?
?
Where: K = 1
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
R HI1 + R EXT1 R LO1 + R EXT1 ?
?
K = ---------- ? R SET ? ------------------------------ ? -----------------------------------------------------------------------------------------------------------
DCR CORE V IN – N ? V CORE V CORE
I OCP
2 ? L CORE ? f S
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
R HI2 + R EXT2 R LO2 + R EXT2 ?
?
FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance (P DR_UP ) the lower drive path resistance
(P DR_UP ) and in the boot strap diode (P BOOT ). The rest of
the power will be dissipated by the external gate resistors
(R G1 and R G2 ) and the internal gate resistors (R GI1 and
R GI2 ) of the MOSFETs. Figures 18 and 19 show the typical
upper and lower gate drives turn-on transition path. The total
power dissipation in the controller itself, P DR , can be roughly
estimated as Equation 30:
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
3
P Qg_Q1
P BOOT = ---------------------
? R HI1 R LO1 ? P Qg_Q1
3
? R HI2 R LO2 ? P Qg_Q2
2
DC voltage across the North Bridge inductor, which will be
impressed across the ISEN_NB pins without any gain. So,
the R 2 resistor for the North Bridge inductor RC filter is left
unpopulated and K = 1.
1. Choose a capacitor value for the North Bridge RC filter. A
0.1μF capacitor is a recommended starting point.
2. Calculate the value for resistor R 1 using Equation 32:
L NB (EQ. 32)
= --------------------------------------
NB
3. Calculate the value for the R SET resistor using
Equation 33: (Derived from Equation 20).
3 100 μ A NB
(EQ. 33)
4. Using Equation 34 (also derived from Equation 20),
calculate the value of K for the Core regulator.
3 N 100 μ A
400
+ --------------------------------------------- ? --------------------
CORE V IN
(EQ. 34)
5. Choose a capacitor value for the Core RC filters. A 0.1μF
R EXT1 = R G1 + -------------
R EXT2 = R G2 + -------------
R GI1
N Q1
R GI2
N Q2
capacitor is a recommended starting point.
(EQ. 30)
Inductor DCR Current Sensing Component
Selection and R SET Value Calculation
With the single R SET resistor setting the value of the
effective internal sense resistors for both the North Bridge
27
FN9278.5
May 17, 2011
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