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参数资料
| 型号： | ISL6323EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 33/36页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL6323 |
| 标准包装： | 1 |
| 系列： | * |
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ISL6323
0.3
I L(P-P) = 0
I L(P-P) = 0.25 I O
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
most critical because they switch large amounts of energy. Next
are small signal components that connect to sensitive nodes or
supply critical bypassing current and signal coupling.
The power components should be placed first, which include
0.2
0.1
the MOSFETs, input and output capacitors, and the inductors. It
is important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally
across all power trains. Equidistant placement of the controller
to the CORE and NB power trains it controls through the
integrated drivers helps keep the gate drive traces equally
short, resulting in equal trace impedances and similar drive
capability of all sets of MOSFETs.
0
0 0.2 0.4 0.6 0.8
DUTY CYCLE (V IN/ V O )
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
0.3
0.2
1.0
When placing the MOSFETs try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally
possible. Input high-frequency capacitors, C HF , should be
placed close to the drain of the upper FETs and the source of
the lower FETs. Input bulk capacitors, CBULK, case size
typically limits following the same rule as the high-frequency
input capacitors. Place the input bulk capacitors as close to the
drain of the upper FETs as possible and minimize the distance
to the source of the lower FETs.
Locate the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency output decoupling
capacitors (ceramic) should be placed as close as practicable
to the decoupling target, making use of the shortest connection
0.1
I L(P-P) = 0
paths to any internal planes, such as vias to GND next or on the
capacitor solder pad.
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
0
0 0.2 0.4 0.6 0.8
DUTY CYCLE (V IN/ V O )
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Layout Considerations
1.0
The critical small components include the bypass capacitors
(C FILTER ) for VCC and PVCC, and many of the components
surrounding the controller including the feedback network and
current sense components. Locate the VCC/PVCC bypass
capacitors as close to the ISL6323 as possible. It is especially
important to locate the components associated with the
feedback circuit close to their respective controller pins, since
they belong to a high-impedance circuit loop, sensitive to EMI
MOSFETs switch very fast and efficiently. The speed with which
the current transitions from one device to another causes
voltage spikes across the interconnecting impedances and
parasitic circuit elements. These voltage spikes can degrade
efficiency, radiate noise into the circuit and lead to device
overvoltage stress. Careful component selection, layout, and
placement minimizes these voltage spikes. Consider, as an
example, the turnoff transition of the upper PWM MOSFET.
Prior to turnoff, the upper MOSFET was carrying channel
current. During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET. Any
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful component
selection, tight layout of the critical components, and short, wide
circuit traces minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC/DC converter
using a ISL6323 controller. The power components are the
33
pick-up.
A multi-layer printed circuit board is recommended. Figure 27
shows the connections of the critical components for the
converter. Note that capacitors C IN and C OUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underneath the component side of the
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from the
PHASE terminal to output inductors short. The power plane
should support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase nodes. Use the remaining printed circuit layers for
small signal wiring.
FN9278.5
May 17, 2011
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| ISL6324ACRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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