参数资料
| 型号： | ISL6323IRZ |
| 厂商： | Intersil |
| 文件页数： | 25/36页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM MONO 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6323
all, there are some pin connections that must be made in
order for the ISL6323 to function properly. The ISEN_NB+
(pin 2) and ISEN_NB- (pin 47) pins as well as the RGND_NB
pin (pin 3) must be tied to ground. A small trace from the pin
to the ground pad under the part is all that is required. The
PVCC_NB pin (pin 42) should be tied to either +5V or to
+12V with a small decoupling capacitor to ground. All other
pins associated with the North Bridge regulator may be left
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I M , V D(ON) , the switching
frequency, f S , and the length of dead times, t d1 and t d2 , at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
? ? ------ + I ----------- ? ? t
? I ?
? I
?
+ ? ------ – ----------- ? ? t
M
P-P
2 ? ?
? N
unconnected.
General Design Guide
This design guide is intended to provide a high-level
P
LOW , 2
= V
D ( ON )
? f
S
M P-P
? N 2 ?
d1
?
I
d2
(EQ. 22)
I P-P
I M
P UP ( 1 ) ≈ V IN ? ? ------ + ---------- ? ? ? ---- 1 ? ? f S
? t ?
P UP ( 2 ) ≈ V IN ? ? ------ – ---------- ? ? ? ---- 2 ? ? f S
P UP ( 3 ) = V IN ? Q rr ? f S
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials,
and example board layouts for all common microprocessor
applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat
dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(r DS(ON) ). In Equation 21, I M is the maximum continuous
output current, I P-P is the peak-to-peak inductor current (see
Equation 2), and d is the duty cycle (V OUT /V IN ).
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P LOW,1 and P LOW,2 .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the upper
MOSFET losses are due to currents conducted across the
input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse
recovery charge, Q rr , and the upper MOSFET r DS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 23,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP(1) .
(EQ. 23)
? N 2 ? ? 2 ?
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 24, the
approximate power loss is P UP(2) .
? I M I P-P ? ? t ? (EQ. 24)
? N 2 ? ? 2 ?
A third component involves the lower MOSFET
reverse-recovery charge, Q rr . Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P UP(3) as shown in
Equation 25.
(EQ. 25)
? I M ? 2
I L ( P-P ) ? ( 1 – d )
P LOW , 1 = r DS ( ON ) ? ? ------ ? ? ( 1 – d ) + -------------------------------------------
25
2
? N ? 12
(EQ. 21)
FN9278.5
May 17, 2011
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| ISL6323IRZ-T | 功能描述:IC HYBRID CTRLR PWM MONO 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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