参数资料
| 型号： | ISL6323IRZ |
| 厂商： | Intersil |
| 文件页数： | 30/36页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM MONO 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页第32页第33页第34页第35页第36页
ISL6323
-------------------------------- > f 0
C 2 (OPTIONAL)
Case 1:
1
2 ? π ? L ? C
R C = R FB ? --------------------------------------------------------
0.66 ? V
0.66 ? V IN
2 ? π ? V P-P ? R FB ? f 0
R C
C C
COMP
FB
2 ? π ? f 0 ? V pp ? L ? C
IN
C C = ------------------------------------------------------
-------------------------------- ≤ f 0 < -------------------------------------
V P-P ? ( 2 ? π ) 2 ? f 02 ? L ? C
R FB
VSEN
ISL6323
Case 2:
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
0.66 ? V
R C = R FB ? ------------------------------------------------------------------
IN
(EQ. 51)
0.66 ? V IN
C C = ---------------------------------------------------------------------------------------
P-P ? R FB ?
( 2 ? π ) 2 ? f 2 ? V L ? C
FIGURE 22. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6323 CIRCUIT
0
f 0 > -------------------------------------
R C = R FB ? ---------------------------------------------
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
Case 3:
1
2 ? π ? C ? ESR
2 ? π ? f 0 ? V pp ? L
0.66 ? V IN ? ESR
0.66 ? V IN ? ESR ? C
2 ? π ? V P-P ? R FB ? f 0 ? L
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f 0 .
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
C C = ------------------------------------------------------------------
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type-III controller, as shown in Figure 23, provides the
necessary compensation.
C 2
equations for the compensation components.
R C
C C
COMP
In Equation 51, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V P-P is the
peak-to-peak sawtooth signal amplitude as described in the
C 1
R 1
R FB
FB
ISL6323
Once selected, the compensation values in Equation 51
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
Equation 51 unless some performance issue is noted.
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 22). Keep
a position available for C 2 , and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
30
VSEN
FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, f HF . This pole can be used for added
noise rejection or to assure adequate attenuation at the error
amplifier high-order pole and zero frequencies. A good general
rule is to choose f HF = 10f 0 , but it can be higher if desired.
Choosing f HF to be lower than 10f 0 can cause problems with
too much phase shift below the system bandwidth as shown in
Equation 52.
FN9278.5
May 17, 2011
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6324AIRZ | IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324IRZ | IC HYBRID CTRLR PWM DUAL 48-QFN |
| ISL6326BIRZ | IC REG CTRLR BUCK PWM VM 40-QFN |
| ISL6326IRZ | IC REG CTRLR BUCK PWM VM 40-QFN |
| ISL6327AIRZ | IC REG CTRLR BUCK PWM 48-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6323IRZ-T | 功能描述:IC HYBRID CTRLR PWM MONO 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE+NORTHBRIDGE, PROG PSI, 3.4MHZ SVI - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324ACRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT., CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ SVI, 5 - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
发布紧急采购，3分钟左右您将得到回复。