参数资料
型号: ISL6323IRZ
厂商: Intersil
文件页数: 29/36页
文件大小: 0K
描述: IC HYBRID CTRLR PWM MONO 48-QFN
标准包装: 43
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6323
V IN
L
Inductor DCR Current Sensing Component Fine
Tuning
I
n
UGATE(n)
4. Replace R 1 and R 2 with the new values and check to see
that the error is corrected. Repeat the procedure if
necessary.
MOSFET
L
DCR
V OUT
DRIVER
LGATE(n)
INDUCTOR
V L (s)
C OUT
Δ V 1
Δ V 2
V C (s)
V OUT
R 1
C
ISL6323 INTERNAL CIRCUIT
I n
SAMPLE
R 2
Δ I
I TRAN
+
-
V C (s)
ISENn-
FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR
Loadline Regulation Resistor
{
V DROOP
R FB = ----------------------------------------------------------------------
(EQ. 50)
I OUT
---------- ? -------------------------- ? --------------- ? K
R SET
I SEN
TO ACTIVE
CORE CHANNELS
TO NORTH BRIDGE
R ISEN
ISENn+
VCC
RSET
R SET
C SET
The loadline regulation resistor, labeled R FB in Figure 8,
sets the desired loadline required for the application.
Equation 50 can be used to calculate R FB .
MAX
400 MAX DCR
3 N
FIGURE 20. DCR SENSING CONFIGURATION
Due to errors in the inductance and/or DCR it may be
necessary to adjust the value of R 1 and R 2 to match the time
constants correctly. The effects of time constant mismatch
can be seen in the form of droop overshoot or undershoot
during the initial load transient spike, as shown in Figure 21.
Follow the steps below to ensure the RC and inductor
L/DCR time constants are matched accurately.
1. If the regulator is not utilizing droop, modify the circuit by
placing the frequency set resistor between FS and
Ground for the duration of this procedure.
2. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
3. Record Δ V1 and Δ V2 as shown in Figure 21. Select new
values, R 1(NEW) and R 2(NEW ) for the time constant
resistors based on the original values, R 1(OLD) and
R 2(OLD) using Equations 48 and 49.
Where K is defined in Equation 7.
If no loadline regulation is required, FS resistor should be
tied between the FS pin and VCC. To choose the value for
R FB in this situation, please refer to “Compensation Without
Compensation With Loadline Regulation
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R C and C C .
Δ V 1
Δ V 2
R 2 ( NEW ) = R 2 ( OLD ) ? ----------
R 1 ( NEW ) = R 1 ( OLD ) ? ----------
Δ V 1
Δ V 2
29
(EQ. 48)
(EQ. 49)
FN9278.5
May 17, 2011
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