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| 型号： | ISL6326CRZ |
| 厂商： | Intersil |
| 文件页数： | 20/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 25% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6326
t d1 is a fixed delay with the typical value as 1.36ms. t d3 is
determined by the fixed 85μs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum t d3 is about 86μs.
During t d2 and t d4 , ISL6326 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R SS from SS pin to GND. The
second soft-start ramp time t d2 and t d4 can be calculated
based on Equations 15 and 16:
when an undervoltage or overvoltage condition is detected,
or the controller is disabled by a reset from EN_PWR,
EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6326
overvoltage protection (OVP) circuit will be active after its
t d2 = ------------------------ ( μ s )
t d4 = ------------------------------------------------ ( μ s )
1.1xR SS
6.25x25
( V VID – 1.1 ) xR SS
6.25x25
(EQ. 15)
(EQ. 16)
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during
the soft-start intervals t d1 , t d2 and t d3 , the OVP threshold is
1.275V. Once the controller detects valid VID input, the OVP
trip point will be changed to DAC + 175mV.
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t d2 will be 704μs and the
second soft-start ramp time t d4 will be 256μs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t d5 . The
typical value for t d5 is 85μs.
V OUT , 500mV/DIV
Two actions are taken by the ISL6326 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (>20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC + 75mV, PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both
upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6326 will again command the lower
MOSFETs to turn on. The ISL6326 will continue to protect
the load in this fashion as long as the overvoltage condition
t d1
t d2
t d3
t d4
t d5
occurs.
EN_VTT
VR_RDY
500μs/DIV
FIGURE 8. SOFT-START WAVEFORMS
Fault Monitoring and Protection
The ISL6326 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6326 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
VID codes will not reset the controller..
VR_RDY
UV
50%
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC
+
85μA
I AVG
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
VDIFF
+
-
OV
during shutdown and releases high after a successful
soft-start and a fixed delay t d5 . VR_RDY will be pulled low
20
VID + 0.175V
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
FN9262.1
May 5, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6326CRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326CRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6326CRZ-T W/GOLD BOND WIRE ONLY - Tape and Reel |
| ISL6326IRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326IRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6327ACRZ | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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