参数资料
| 型号： | ISL6336BIRZ |
| 厂商： | Intersil |
| 文件页数： | 20/31页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
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ISL6336B
V IMON = ------------------- ? ------------------ ? I OUT
R ISEN
When all conditions above are satisfied, ISL6336B begins
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6336B reads the VID
code at VID input pins. If the VID code is valid, ISL6336B will
regulate the output to the final VID setting. If the VID code is
an OFF code, ISL6336B will shut down, and cycling VCC,
EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6336B based VR has 4 periods during soft-start as
shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, The controller will have fixed
delay period t D1 . After this delay period, the VR will begin
first soft-start ramp until the output voltage reaches 1.1V
V BOOT voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period t D3 . At the end of t D3
period, ISL6336B reads the VID signals. If the VID code is
valid, ISL6336B will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus the offset voltage.
V OUT, 500mV/DI V
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t D2 will be 704μs and the
second soft-start ramp time t D4 will be 256μs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t D5 . The
typical value for t D5 is 85μs. Before VR_RDY is released,
the controller disregards the PSI# input and always operates
in normal CCM PWM mode.
Current Sense Output
The current sourced at the IMON pin is equal to the sensed
average current inside the ISL6336B, I AVG . In a typical
application, a resistor is placed from the IMON pin to GND to
generate a voltage which is proportional to the load current
as shown in Equation 17:
R IMON R X (EQ. 17)
N
where V IMON is the voltage at the IMON pin, R IMON is the
resistor between IMON and GND, I OUT is the total output
current of the converter, R ISEN is the sense resistor
connected to the ISEN+ pin, N is the active channel number
and R X is the DC resistance of the current sense element.
The resistor from the IMON pin to GND should be chosen to
t D1
t D2
t D3 t D4
t D5
ensure that the voltage at the IMON pin is less than 1.12V
under the maximum load current. The IMON pin voltage is
EN_VTT
VR_RDY
500μs/DIV
FIGURE 9. SOFT-START WAVEFORMS
The soft-start time is the sum of the 4 periods as shown in
Equation 14:
clamped at a maximum of 1.12V. Once the 1.12V threshold
is reached, an overcurrent shutdown will be initiated as
A small capacitor can be placed between the IMON pin and
GND to reduce noise. In addition, some applications will
require the V IMON signal to be filtered with a minimum time
constant. The filter capacitor can be chosen appropriately
based on the R IMON value to set the desired time constant.
t SS = t D1 + t D2 + t D3 + t D4
(EQ. 14)
t D1 is a fixed delay with a typical value as 1.36ms. t D3 is
determined by a fixed 85μs plus the time to obtain valid VID
voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum t D3 is about 86μs.
During t D2 and t D4 , ISL6336B digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator, which
V IMON_OFS
is defined by a resistor R SS from SS pin to GND or VCC. The
equations are the same for the case where R SS is connected
to GND or VCC. The two soft-start ramp times t D2 and t D4 can
be calculated based on the Equations 15 and 16:
0V
0A LOAD INCREASING
t D2 = ------------------------ ( μ s )
( ( V VID – 1.1 ) ? R SS )
1.1 ? R SS
6.25 ? 25
6.25 ? 25
t D4 = ------------------------------------------------------ ( μ s )
20
(EQ. 15)
(EQ. 16)
FIGURE 10. IMON VOLTAGE vs OUTPUT CURRENT
The voltage at the IMON pin will vary linearly with output
current, as shown in Figure 10 with some tolerance. Some
applications may require the addition of a positive offset on
FN6696.2
August 31, 2010
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相关代理商/技术参数 |
参数描述 |
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| ISL6336BIRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336CRZ | 功能描述:IC CTRLR PWM 6PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336CRZ-T | 功能描述:IC CTRLR PWM 6PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336IRZ | 功能描述:IC CTRLR PWM 6PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336IRZ-T | 功能描述:IC CTRLR PWM 6PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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