参数资料
型号: ISL6336BIRZ
厂商: Intersil
文件页数: 9/31页
文件大小: 0K
描述: IC CTRLR PWM SYNC BUCK 48-QFN
标准包装: 43
应用: 控制器,Intel VR11.1
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
产品目录页面: 1248 (CN2011-ZH PDF)
ISL6336B
Electrical Specifications
Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued)
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 7)
TYP
(Note 7) UNITS
Peak Current Limit for Individual Channel
IMON Voltage Clamp and OCP Trip Level
115
1.085
129
1.11
146
1.14
μA
V
THERMAL MONITORING AND FAN CONTROL
TM Input Voltage for VR_HOT Trip
TM Input Voltage for VR_HOT Reset
32.9
38.7
33.3
39.1
33.7
39.6
%VCC
%VCC
Leakage Current of VR_HOT
VR_HOT Low Voltage
With external pull-up resistor connected to VCC
With 1.24k Ω resistor pull-up to VCC, I VR_HOT = 4mA
-
-
-
-
5
0.3
μA
V
VR READY AND PROTECTION MONITORS
Leakage Current of VR_RDY
VR_RDY Low Voltage
Undervoltage Threshold
VR_RDY Reset Voltage
Overvoltage Protection Threshold
With external pull-up resistor connected to VCC
I VR_RDY = 4mA
VDIFF Falling
VDIFF Rising
Before valid VID
-
-
48
57
1.250
-
-
50
59.6
1.273
5
0.3
52
62
1.300
μA
V
%VID
%VID
V
Overvoltage Protection Reset Hysteresis
After valid VID, the voltage above VID
158
-
175
100
190
-
mV
mV
OVP Output Low Voltage
IOVP = 4mA
-
0.106
0.16
V
NOTES:
3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
4. Limits are established by characterization and are not production tested.
5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID input.
6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
9
FN6696.2
August 31, 2010
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