参数资料
型号: ISL6353CRTZ-T
厂商: Intersil
文件页数: 28/30页
文件大小: 0K
描述: IC CONTROLLER DDR VR12 40TQFN
标准包装: 6,000
应用: 控制器,DDR,Intel VR12
输入电压: 4.5 V ~ 25 V
输出数: 1
输出电压: 0.25 V ~ 1.52 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
ISL6353
Layout Guidelines (Continued)
ISL6353
PIN NUMBER
10, 11, 12
13, 14, 15
SYMBOL
COMP, FB,
FB2
ISEN3,
LAYOUT GUIDELINES
Place the compensator components in general proximity of the controller
Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN, then through another capacitor (Cvsumn) to GND. Place
ISEN2, ISEN1 Cisen capacitors as close as possible to the controller and keep the following loops small:
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops that need to minimized.
ISEN3
Phase1
Risen
L3
Ro
Cisen
Phase2
Risen
L2
Ro
Vo
ISEN2
Cisen
Phase3
Risen
L1
Ro
ISEN1
GND
Cisen
Vsumn
Cvsumn
16, 17
18, 19
20
21
VSEN, RTN
ISUMN,
ISUMP
VDD
VIN
Place the VSEN/RTN filter in close proximity of the controller for good decoupling. Route these signals differentially
from the remote sense location back to the controller.
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to the phase 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces
in parallel fashion.
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces
on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is
allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings
show the two preferred ways of routing current sensing traces. If possible connect the traces to the inductor pad in only
one place and isolate this connection from other planes of the same net that may be present on other layers. Also make
the connections a symmetric as possible for all phases.
Inductor
Inductor
Vias
Current-Sensing
Current-Sensing
Traces
Traces
Place the decoupling capacitor a close as possible to this pin.
Place the decoupling capacitor a close as possible to this pin.
28
September 15, 2011
FN6897.0
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