参数资料
| 型号： | ISL6353IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/30页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER DDR VR12 40TQFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR，Intel VR12 |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.25 V ~ 1.52 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
ISL6353
V crs
i L
CCM/DCM BOUNDARY
VW
VDD
VR_ON
DAC
1.3ms
2.5mV/μs
VBOOT
V crs
VW
LIGHT DCM
PGOOD
READY FOR SVID COMMAND
FIGURE 8. SOFT-START WAVEFORMS
i L
DEEP DCM
Voltage Regulation and Differential Sensing
V crs
VW
After the start sequence, the ISL6353 regulates the output voltage
to the value set by the SetVID commands through the SVID bus or
to the value set by the status of the VSET1/2 pins. The ISL6353
will regulate the output voltage to VID + OFFSET (Register 33h). A
iL
FIGURE 7. PERIOD STRETCHING
Figure 7 shows the principle of operation in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
differential amplifier allows remote voltage sensing for precise
voltage regulation.
VID Table
The ISL6353 will regulate the output voltage to VID+OFFSET (33h).
Table 1 shows the output voltage setting based on the VID register
setting.
window size and therefore it is the same, making the inductor
current triangle the same in the three cases. The ISL6353 clamps
the ripple capacitor voltage V crs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V crs ,
naturally stretching the switching period. The inductor current
VID7
0
VID6
0
VID5
0
TABLE 1. VID TABLE
VID4 VID3 VID2 VID1
0 0 0 0
VID0
0
V O
Hex (V)
0 0 0.0000
triangles move further apart from each other such that the
inductor current average value is equal to the load current. The
reduced switching frequency helps increase light load efficiency.
Start-up Timing
With the controller's V DD voltage above the POR threshold, the
start-up sequence begins about 1.3ms after VR_ON exceeds the
logic high threshold. The ISL6353 uses digital soft-start to ramp
up the DAC to the boot voltage, V BOOT . V BOOT is set by the PROG2
pin resistor and the status of the VSET1/2 pins. The DAC slew
rate during soft-start is about 2.5mV/μs. PGOOD is asserted high
at the end of the start-up sequence indicating that the output
voltage has moved to the V BOOT setting, the VR is operating
properly and all phases are switching. Figure 8 shows the typical
start-up timing.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 1 0.2500
0 2 0.2550
0 3 0.2600
0 4 0.2650
0 5 0.2700
0 6 0.2750
0 7 0.2800
0 8 0.2850
0 9 0.2900
0 A 0.2950
0 B 0.3000
0 C 0.3050
0 D 0.3100
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0 E
0 F
0.3150
0.3200
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1 0 0.3250
1 1 0.3300
1 2 0.3350
1 3 0.3400
1 4 0.3450
1 5 0.3500
13
September 15, 2011
FN6897.0
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