参数资料
| 型号： | ISL6353IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 26/30页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER DDR VR12 40TQFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR，Intel VR12 |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.25 V ~ 1.52 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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ISL6353
VSET1 and VSET2 can be used to set the output voltage of the
regulator. Table 9 shows the available options. If VSET1 and VSET2
are connected to ground, the controller will refer only to the SVID
register setting to program the output voltage. If any other logic
combination is used on VSET1/2, the controller will ignore the
SVID register setting and program the output voltage based on
Table 8 for soft-start and steady state.
Supported Serial VID Data And Configuration
Registers
The controller supports the following data and configuration
registers.
TABLE 11. SUPPORTED DATA AND CONFIGURATION
REGISTERS
TABLE 9. VSET1/2 PIN DEFINITION
REGISTER
DEFAULT
V BOOT
from PROG2
(V)
VSET1
VSET2
OUTPUT
VOLTAGE
INDEX
00h
NAME
Vendor ID
DESCRIPTION
Uniquely identifies the VR
vendor. Assigned by Intel.
VALUE
12h
1.5
0
0
SVID Setting
01h
Product ID
Uniquely identifies the VR
35h
1.5
0
1
1.35V
product. Intersil assigns this
number.
1.5
1.5
1.35
1.35
1
1
0
0
0
1
0
1
1.6V
1.65V
SVID Setting
1.2V
02h
05h
Product
Revision
Protocol ID
Uniquely identifies the revision
of the VR control IC. Intersil
assigns this data.
Identifies which revision of SVID 01h
protocol the controller supports.
1.35
1
0
1.4V
06h
Capability
Identifies the SVID VR
81h
1.35
1.2
1
0
1
0
1.45V
SVID Setting
capabilities and which of the
optional telemetry registers are
supported.
1.2
1.2
1.2
0
0
0
1
1
0
0
1
0
1
0
1
1.1V
1.25V
1.3V
SVID Setting
1.05V
10h
11h
Status_1
Status_2
Data register read after ALERT# 00h
signal; indicating if a VR rail has
settled, has reached VRHOT
condition or has reached ICC
max.
Data register showing Status_2 00h
communication.
0
0
1
1
0
1
1.55V
1.15V
12h
Temperature
Zone
Data register showing
temperature zones that have
been entered.
00h
The PSI pin can be used to set the power state of the regulator as
indicated on Table 10. If PSI is connected to ground the controller
will refer only to the SVID register contents to set the power state. If
15h
IOUT
Data register showing output
current information. The voltage
at the IMON pin is digitized and
00h
PSI is pulled high, the controller will enter the PS2 state. If PSI is
stored in this register.
connected to a high impedance, the controller will enter the PS1
state.
TABLE 10. PSI PIN DEFINITION
1Ch
Status_2_
LastRead
This register contains a copy of 00h
the Status_2 data that was last
read with the GetReg (Status_2)
command.
PSI
0
High-Z
1
ADDRESS
Internal SVID Power State
PS1
PS2
21h
ICC max
Data register containing the ICC Refer to
max the platform supports; set Table 6
at start-up by resistor on PROG1
pin. The platform design
engineer programs this value
during the design process.
Binary format in amps, for
example 100A = 64h.
24h
SR-fast
Slew Rate Normal. The fastest
0Ah
slew rate the platform VR can
sustain. Binary format in
mV/μs. i.e. 0Ah = 10mV/μs.
26
25h
SR-slow
Is 4x slower than normal. Binary 02h
format in mV/μs. i.e.
02h = 2.5mV/μs
September 15, 2011
FN6897.0
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