参数资料
| 型号： | ISL6353IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/30页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER DDR VR12 40TQFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR，Intel VR12 |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.25 V ~ 1.52 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
ISL6353
I IMON = --- × I sense
1
Current Monitor
The ISL6353 provides a current monitor function. The IMON pin
outputs a high-speed analog current source that is 1/4 times the
I sense current.
(EQ. 21)
4
time constant for R s C s should be used such that the ISEN
voltages have minimal ripple and represent the DC current
flowing through the inductors. Recommended values are
R s = 10k Ω and C s = 0.22μF.
R s should be routed to the inductor phase-node pad in order to
help eliminate the effect of phase node parasitic PCB DCR.
Equations 26 through 28 give the ISEN pin voltages:
A resistor R imon is connected to the IMON pin to convert the
IMON pin current to a voltage. The voltage across R imon is
expressed in Equation 22:
V ISEN1 = ( R dcr1 + R pcb1 ) × I L1
(EQ. 26)
V Rimon = --- × I
1
4
sense
× R imon
(EQ. 22)
V ISEN2 = ( R dcr2 + R pcb2 ) × I L2
(EQ. 27)
Substitution of Equation 14 into Equation 22 gives Equation 23:
V ISEN3 = ( R dcr3 + R pcb3 ) × I L3
(EQ. 28)
V Rimon = --------- × ----------------------------------------- × ------------ × I o × R imon
R sum
4R i
1 R ntcnet DCR
N
N
R ntcnet + --------------
1
V Rimon × R i × ( NR ntcnet + R sum )
R imon = ----------------------------------------------------------------------------------------
4
--- R ntcnet × DCR × I o
(EQ. 23)
(EQ. 24)
where R dcr1 , R dcr2 and R dcr3 are inductor DCR; R pcb1 , R pcb2
and R pcb3 are parasitic PCB DCR between the inductor output
pad and the output voltage rail; and I L1 , I L2 and I L3 are inductor
average currents.
The ISL6353 will adjust the phase pulse-width relative to the
other phases to make V ISEN1 = V ISEN2 = V ISEN3 , thus to achieve
I L1 = I L2 = I L3 , when R dcr1 = R dcr2 = R dcr3 and
R pcb1 = R pcb2 = R pcb3 .
V Rimon × R i × ? N --------------------------------------------------- + R sum ?
? R ntcs + R ntc + R p ?
R imon = ------------------------------------------------------------------------------------------------------------------------
--- ( R ntcs + R ntc ) × R p
------------------------------------------------------- × DCR × I omax
Rpcb3
V3n
Substitution of Equation 5 and application of the full load
condition in Equation 24 gives Equation 25:
? ( R ntcs + R ntc ) × R p ?
(EQ. 25)
1
4
R ntcs + R ntc + R p
where I omax is the full load current.
Using the same components for L1, L2 and L3 will provide a good
match of R dcr1 , R dcr2 and R dcr3 . Board layout will determine
R pcb1 , R pcb2 and R pcb3 . Each phase should be as symmetric as
possible in the PCB layout for the power delivery path between
each inductor and the output voltage load, such that
R pcb1 = R pcb2 = R pcb3 .
L3 Rdcr3
V3p
Phase3
Rs
ISEN3 IL3
Rs
Cs
V2n
A capacitor C imon can be paralleled with R imon to filter the IMON
pin voltage. The R imon C imon time constant is the user’s choice.
The time constant should be long enough such that switching
frequency ripple is removed.
INTERNAL
TO IC
ISEN2
Rs
Phase2
Rs
Rs
Cs
V2p
L2
Rdcr2 Rpcb2
IL2
Vo
V1n
Phase Current Balancing
L3
Phase3
Rs
ISEN3
IL3
Rdcr3
Rpcb3
ISEN1
Rs
V1p
Phase1
Rs
Rs
Cs
L1
Rdcr1
IL1
Rpcb1
INTERNAL
TO IC
ISEN2
Cs
Phase2
Rs
Cs
Phase1
L2
L1
IL2
Rdcr2
Rdcr1
Rpcb2
Rpcb1
Vo
Rs
FIGURE 13. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
Sometimes, it is difficult to implement a symmetric layout. For
ISEN1
Rs
Cs
IL1
the circuit shown in Figure 12, an asymmetric layout causes
different R pcb1 , R pcb2 and R pcb3 resulting in phase current
imbalance. Figure 13 shows a differential-sensing current
FIGURE 12. CURRENT BALANCING CIRCUIT
The ISL6353 monitors individual phase current by monitoring the
ISEN1, ISEN2, and ISEN3 pin voltages. Figure 12 shows the
current balancing circuit recommended for the ISL6353. Each
phase node voltage is averaged by a low-pass filter consisting of
R s and C s , and presented to the corresponding ISEN pin. A long
21
balancing circuit recommended for the ISL6353. The current
sensing traces should be routed to the inductor pads so they only
pick up the inductor DCR voltage. Each ISEN pin sees the average
voltage of three sources: its own phase inductor phase-node pad,
September 15, 2011
FN6897.0
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