参数资料
| 型号： | ISL6406IV-T |
| 厂商： | Intersil |
| 文件页数： | 10/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 770kHz |
| 占空比： | 100% |
| 电源电压： | 2.97 V ~ 3.63 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
ISL6406
Dedicate one solid layer, usually a middle layer of the PC
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into
OSC
PWM
COMPARATOR
DRIVER
V IN
L O
V OUT
smaller islands of common voltage levels. Keep the metal
runs from the PHASE terminals to the output inductor short.
Δ V OSC
-
+
DRIVER
PHASE
C O
The power plane should support the input power and output
power nodes. Use copper-filled polygons on the top and
bottom circuit layers for the phase nodes. Use the remaining
Z FB
ESR
(PARASITIC)
printed circuit layers for small signal wiring. The wiring traces
from the GATE pins to the MOSFET gates should be kept
V E/A
-
+
Z IN
short and wide enough to easily handle the 1A of drive
ERROR
REFERENCE
current. The switching components should be placed close
to the ISL6406 first. Minimize the length of the connections
AMP
DETAILED COMPENSATION COMPONENTS
between the input capacitors, C IN , and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain and
islands as possible. Position the output inductor and output
C 2
C 1
R 2
Z FB
C 3
Z IN
R 3
V OUT
capacitors between the upper and lower MOSFETs and the
load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, C BP , close to
the VCC pin with a via directly to the ground plane. Place
the PWM converter compensation components close to the
COMP
-
+
ISL6406 REFERENCE
FB
R 1
FB and COMP pins. The feedback resistors for both
regulators should also be located as close as possible to
the relevant FB pin with vias tied straight to the ground
plane as required.
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
f LC = ----------------------------
f ESR = ---------------------------------------
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V E/A ) is compared with the
1
2 π L O C O
1
2 π ( ESR ) ( C O )
(EQ. 4)
(EQ. 5)
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with a peak amplitude of V IN at the
PHASE node. The PWM wave is smoothed by the output
filter (L and C O ).The modulator transfer function is the
small-signal transfer function of V OUT /V E/A . This function is
dominated by a DC Gain and the output filter (L O and C O ),
with a double pole break frequency at F LC and a zero at
F ESR . The DC Gain of the modulator is simply the input
voltage (V IN ) divided by the peak-to-peak oscillator voltage,
V OSC .
10
The compensation network consists of the error amplifier
(internal to the ISL6406) and the impedance networks Z IN
and Z FB .The goal of the compensation network is to provide
a closed-loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase
margin is the difference between the closed loop phase at
f 0dB and 180°.
Equations 4 and 5 relate the compensation network’s poles,
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 and
C 3 ) in Figure 7. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place first zero below filter ’s double pole (~75% F LC ).
3. Place second zero at filter ’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier ’s open-loop gain.
7. Estimate phase margin—repeat if necessary.
FN9073.8
September 4, 2009
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6410IU-TK | IC REG BUCK SYNC 0.6A 10MSOP |
| ISL6412IRZ-TK | IC REG LDO 1.8V/2.8V/2.8V 16-QFN |
| ISL6414IRZ | IC REG LDO TRPL OUTP 16QFN |
| ISL6416IA-TK | IC REG LDO 1.8V/2.8V/2.8V 16QSOP |
| ISL6420AIR-TK | IC REG CTRLR BUCK PWM VM 20-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6406IVZ | 功能描述:电压模式 PWM 控制器 VER OF ISL6406IV RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6406IVZ-T | 功能描述:电压模式 PWM 控制器 VER OF ISL6406IV-T RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6406MREPZ | 制造商:Intersil Corporation 功能描述:V62/08610-01XE, -55 TO 125C PB-FREE VID VERSION OF THE ISL64 - Rail/Tube |
| ISL6406MREPZ-TK | 制造商:Intersil Corporation 功能描述:V62/08610-01XE, -55 TO 125C PB-FREE VID VERSION OF THE ISL64 - Tape and Reel |
| ISL6406MVEP | 制造商:Intersil Corporation 功能描述:SOFT SW PWM CNTRLR 1-OUT SYNCH BUCK PWM CNTRLR 3.3V/5V 100KH - Rail/Tube |
发布紧急采购，3分钟左右您将得到回复。