参数资料
型号: ISL6406IV-T
厂商: Intersil
文件页数: 8/17页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16TSSOP
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 770kHz
占空比: 100%
电源电压: 2.97 V ~ 3.63 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 带卷 (TR)
ISL6406
.
+3.3V
converter ’s efficiency and reduces cost by eliminating a
current sensing resistor. The over current function cycles the
soft-start function in a hiccup mode to provide fault
VCC
CPVOUT
BOOT
D1
VIN
protection. A resistor (r OCSET ) programs the over current
trip level (see Typical Application diagrams beginning on
page 3). An internal 20μA (typical) current sink develops a
voltage across r OCSET that is referenced to V IN . When the
voltage across the upper MOSFET (also referenced to V IN )
ISL6406
UGATE
PHASE
C4
Q1
L OUT
V OUT
exceeds the voltage across r OCSET , the overcurrent function
initiates a soft-start sequence.
LGATE
FB
Q2
+
C OUT
V OUT (2.5V)
COMP
C2
C1
R2
R1
C3
R4
R3
0V
INTERNAL SOFT-START FUNCTION
FIGURE 4. OUTPUT VOLTAGE SELECTION
Frequency Synchronization and Enable
The external frequency synchronization and enable
functions are combined in SYNC/EN pin. This pin is TTL
compatible for VCC = 3.3V or 5V. The device is disabled if
DELAY INTERVAL
the input to this pin is TTL LOW for more than 40μs (typ); it is
t0
t1
t2
enabled if the input is TTL HIGH without delay. When
disabling the IC, the charge pump is turned off and the
BOOT pin is left charged at ~5V. In some cases, this charge
will inadvertently leak through the upper gate driver and can
possibly turn on the upper FET. To avoid this, it is
recommended that a 1M Ω ‘bleed’ resistor be connected from
the BOOT pin to GND. This resistor is shown in the Typical
Application Schematics on page 3 as R BOOT .
The SYNC/EN pin is monitored by the internal timer. The
timer allows SYNC pulses (TTL LOW level) to pass through,
as long as the pulses are shorter than 22μs. The minimum
SYNC pulse width is 40ns (typ).
The oscillator can SYNC to an external frequency of
between 1.1x and 2.0x the free-running frequency. Loop
acquisition time is about 200 clock cycles. The timing
resistor (RT) is always required, regardless of whether
SYNC pulses are being used or not.
For instance, if RT is selected such that the switching
TIME
FIGURE 5. OVERCURRENT PROTECTION RESPONSE
Figure 5 illustrates the protection feature responding to an
overcurrent event. At time t0, an overcurrent condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function begins
producing soft-start ramps. The delay interval seen by the
output is equivalent to three soft-start cycles. The fourth
internal soft-start cycle initiates a normal soft-start ramp of the
output, at time t1. The output is brought back into regulation
by time t2, as long as the overcurrent event has cleared. Had
the cause of the overcurrent still been present after the delay
interval, the overcurrent condition would be sensed and the
regulator would be shut down again for another delay interval
of three soft-start cycles. The resulting hiccup mode style of
protection would continue to repeat indefinitely.
The overcurrent function will trip at a peak inductor current
(I peak ) determined by Equation 3:
r DS ( ON )
frequency is 100kHz then the ISL6406 can be synchronized
to a switching frequency from 110kHz to 200kHz.
Overcurrent Protection
( I OCSET ) ( R OCSET )
I PEAK = --------------------------------------------------------
(EQ. 3)
The overcurrent function protects the converter from a
shorted output by using the upper MOSFET ON-resistance,
r DS(ON) , to monitor the current. This method enhances the
8
where I OCSET is the internal OCSET current source (20μA
typical). The OC trip point varies mainly due to the MOSFET
r DS(ON) variations. To avoid overcurrent tripping in the
FN9073.8
September 4, 2009
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