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参数资料
| 型号： | ISL6420IAZ |
| 厂商： | Intersil |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20-QSOP |
| 标准包装： | 580 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 包装： | 管件 |
ISL6420
F LC = ---------------------------------------
2 π ? L O ? C O
F ESR = ---------------------------------------------
ENSS
ISL6420
BOOT
C BOOT
PHASE
+5V
VCC
D1
+V IN
Q1
Q2
L O
C O
V OUT
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC .
Modulator Break Frequency Equations
1
(EQ. 4)
1
(EQ. 5)
2 π ? ( ESR ? C O )
C SS
GND
C VCC
The compensation network consists of the error amplifier
(internal to the ISL6420) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
DRIVER
COMPARATOR L O
FIGURE 14. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
V IN
OSC
PWM
V OUT
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 o . The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 14. Use these guidelines for
locating the poles and zeros of the compensation network:
Δ V OSC
-
+
DRIVER
PHASE
C O
Compensation Break Frequency Equations
F Z1 = ----------------------------------
Z FB
ESR
(PARASITIC)
1
2 π ? R 2 ? C1
(EQ. 6)
F P1 = -------------------------------------------------------
2 π ? R2 ? ? ---------------------- ?
V E/A
-
+
ERROR
Z IN
REFERENCE
1
C1 ? C2
? C1 + C2 ?
(EQ. 7)
AMP
F Z2 = ------------------------------------------------------
DETAILED COMPENSATION COMPONENTS
1
2 π ? ( R1 + R3 ) ? C3
(EQ. 8)
F P2 = ----------------------------------
C2
Z FB
Z IN
V OUT
1
2 π ? R3 ? C3
(EQ. 9)
C1
R2
C3
R3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1 ST Zero Below Filter ’s Double Pole
COMP
ISL6420
-
+
REF
FB
R1
(~75% F LC )
3. Place 2 ND Zero at Filter ’s Double Pole
4. Place 1 ST Pole at the ESR Zero
5. Place 2 ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier ’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FIGURE 15. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V IN at the
PHASE node. The PWM wave is smoothed by the output filter
(L O and C O ).
The modulator transfer function is the small-signal transfer
function of Vout/V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC Gain of
15
Figure 15 shows an asymptotic plot of the DC/DC
converter ’s gain vs. frequency. The actual Modulator Gain
has a high gain peak do to the high Q factor of the output
filter and is not shown in Figure 15. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F P2
with the capabilities of the error amplifier. The Loop Gain is
constructed on the log-log graph of Figure 15 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
FN9151.5
February 13, 2008
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| ISL6420IAZS2698 | 制造商:Intersil Corporation 功能描述:PB-FREE SYNC BUCK PWM CONT. WITH 4.5V-16V INPUT,20LD QSOP - Rail/Tube |
| ISL6420IAZ-TK | 功能描述:IC REG CTRLR BUCK PWM VM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6420IAZ-TKS2698 | 制造商:Intersil Corporation 功能描述:PB-FREE SYNC BUCK PWM CONT. WITH 4.5V-16V INPUT,20LD QSOP, 1 - Tape and Reel |
| ISL6420IR | 功能描述:IC REG CTRLR BUCK PWM VM 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6420IR-T | 功能描述:IC REG CTRLR BUCK PWM VM 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
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