参数资料
型号: ISL6420IAZ
厂商: Intersil
文件页数: 16/19页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20-QSOP
标准包装: 580
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 100%
电源电压: 4.5 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
包装: 管件
ISL6420
function to the compensation transfer function and plotting
the gain.
transient. An aluminum electrolytic capacitor's ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
100
80
60
F Z1 F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
40
20LOG
capacitor ’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
20
0
-20
-40
(R2/R1)
MODULATOR
GAIN
20LOG
(V IN / Δ V OSC )
COMPENSATION
GAIN
LOOP GAIN
small case size perform better than a single large case
capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
-60
10
100
1k
F LC
10k
F ESR
100k
1M
10M
ripple requirements and minimize the converter ’s response
time to the load transients. The inductor value determines
FREQUENCY (Hz)
FIGURE 16. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
the converter ’s ripple current and the ripple voltage is a
function of the ripple current and the output capacitors ESR.
The ripple voltage and current are approximated by the
following equations:
Δ I L = -------------------------------- ? ----------------
V IN
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with -
20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
V IN - V OUT V OUT
Fs x L
Δ V OUT = Δ I L ? ESR
(EQ. 10)
(EQ. 11)
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
Increasing the value of inductance reduces the ripple current
and voltage. However, larger inductance values reduce the
converter ’s response time to a load transient.
One of the parameters limiting the converter ’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6420 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
t RISE = --------------------------------
t FALL = -------------------------------
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0μF
L O × I TRAN
V IN – V OUT
L O × I TRAN
V OUT
(EQ. 12)
(EQ. 13)
ceramic capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor ’s ESR will determine the output ripple
voltage and the initial voltage drop after a high slew-rate
16
where: I TRAN is the transient load current step, t RISE is the
response time to the application of load, and t FALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
FN9151.5
February 13, 2008
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ISL6420IAZ-TKS2698 制造商:Intersil Corporation 功能描述:PB-FREE SYNC BUCK PWM CONT. WITH 4.5V-16V INPUT,20LD QSOP, 1 - Tape and Reel
ISL6420IR 功能描述:IC REG CTRLR BUCK PWM VM 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR)
ISL6420IR-T 功能描述:IC REG CTRLR BUCK PWM VM 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR)