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参数资料
| 型号： | ISL6420IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 11/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20-QFN |
| 标准包装： | 1,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6420
GPIO1/REFIN
This is a dual function pin. If VMSET/MODE is not connected
to VCC5 then this pin serves as GPIO1. Refer to Table 2 for
GPIO1 commands interpretation.
If VMSET/MODE is connected to VCC5 then this pin will
serve as REFIN. As REFIN, this pin is the non-inverting input
to the error amplifier. Connect the desired reference voltage
to this pin in the range of 0.6V to 1.25V.
Connect this pin to VCC5 to use internal reference.
REFOUT
It provides buffered reference output for REFIN. Connect
reference tracking mode are not needed, this pin can be tied
directly to ground.
GPIO2
This is general purpose IO pin for voltage margining. Refer
to Table 2.
Exposed Thermal Pad
This pad is electrically isolated. Connect this pad to the
signal ground plane using at least five vias for a robust
thermal conduction path.
TABLE 2. VOLTAGE MARGINING CONTROLLED BY
GPIO1/REFIN AND GPIO2
2.2μF decoupling capacitor to this pin.
VMSET/MODE
This pin is a dual function pin. Tie this pin to VCC5 to disable
voltage margining. When not tied to VCC5, this pin serves as
VMSET. Connect a resistor from this pin to ground to set the
delta for voltage margining. If voltage margining and external
GPIO1/REFIN
L
L
H
H
GPIO2
L
H
L
H
VOUT
No Change
+ Delta VOUT
- Delta VOUT
Ignored
TABLE 3. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION
PIN CONFIGURATIONS
FUNCTION/MODES
VMSET/MODE
REFOUT
GPIO1/REFIN
GPIO2
Enable Voltage Margining Pin Connected to GND with
resistor. It is used as VMSET.
Connect a 2.2μF capacitor for Serves as a general
bypass of external reference. purpose I/O. Refer to
Table 2
Serves as a general
purpose I/O. Refer to
Table 2
No Voltage Margining.
H
Connect a 2.2μF capacitor to
H (Note 9)
L
Normal operation with
internal reference.
Buffered V REFOUT = 0.6V.
GND.
No Voltage Margining.
External reference.
Buffered V REFOUT =
H
Connect a 2.2μF capacitor to Connect to an external
GND.
reference voltage source
(0.6V to 1.25V)
L
V REFIN
NOTES:
8. The GPIO1/REFIN and GPIO2 pins cannot be left floating.
9. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
11
FN9151.5
February 13, 2008
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| ISL6421AER-T | 功能描述:IC REG SGL LNB CONTROL 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
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