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参数资料
| 型号： | ISL6420IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 13/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20-QFN |
| 标准包装： | 1,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6420
A small ceramic capacitor should be placed in parallel with
R OCSET to smooth the voltage across R OCSET in the
presence of switching noise on the input voltage.
Voltage Margining
The ISL6420 has a voltage margining mode that can be
used for system testing. The voltage margining percentage
is resistor selectable up to ±10%. The voltage margining
mode can be enabled by connecting a margining set resistor
from VMSET/MODE pin to ground and using the control pins
GPIO1/REFIN and GPIO2 to toggle between positive and
negative margining (Refer to Table 2). With voltage
margining enabled, the VMSET resistor to ground sets a
current, which is switched to the FB pin. The current will be
equal to 2.468V divided by the value of the external resistor
tied to the VMSET/MODE pin.
V OUT
100m/DIV
V OUT
100mV/DIV
2ms/DIV
FIGURE 11. VOLTAGE MARGINING SLEW TIME
I VM = ------------------------
Δ V VM = 2.468V ------------------------
2.468V
R VMSET
R FB
R VMSET
(EQ. 2)
(EQ. 3)
The slew time of the current is set by an external capacitor
on the CDEL pin, which is charged and discharged with a
100 μ A current source. The change in voltage on the
capacitor is 2.5V. This same capacitor is used to set the
PGOOD active delay after soft-start. When PGOOD is low,
The power supply output increases when GPIO2 is HIGH
and decreases when GPIO1/REFIN is HIGH. The amount
that the output voltage of the power supply changes with
voltage margining, will be equal to 2.468V times the ratio of
the external feedback resistor and the external resistor tied
to VMSET/MODE pin. Figure 9 shows the positive and
negative margining for a 3.3V output, using a 20.5k Ω
feedback resistor and using various VMSET resistor values.
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
the internal PGOOD circuitry uses the capacitor and when
PGOOD is high the voltage margining circuit uses the
capacitor. The slew time for voltage margining can be in the
range of 300μs to 2ms.
External Reference/DDR Supply
The voltage margining can be disabled by connecting the
VMSET/MODE to VCC5. In this mode the chip can be
configured to work with an external reference input and
provide a buffered reference output.
If VMSET/MODE pin and the GPIO1/REFIN pin are both tied
to VCC5, then the internal 0.6V reference is used as the
error amplifier non-inverting input. The buffered reference
output on REFOUT will be 0.6V ±0.01V, capable of sourcing
20mA and sinking up to 50μA current with a 2.2μF capacitor
connected to the REFOUT pin.
If VMSET/MODE pin is tied to high but GPIO1/REFIN is
connected to external voltage source between 0.6V to 1.25V,
2.8
150
175
200
225
250 275 300
RVMSET (k Ω )
325
350
375
400
then this external voltage is used as the reference voltage at
the positive input of the error amplifier. The buffered
reference output on REFOUT will be Vrefin ±0.01V, capable
FIGURE 10. VOLTAGE MARGINING vs VMSET RESISTANCE
13
of sourcing 20mA and sinking up to 50μA current with a
2.2μF capacitor on the REFOUT pin.
Power Good
The PGOOD pin can be used to monitor the status of the
output voltage. PGOOD will be true (open drain) when the
FB pin is within ±10% of the reference and the ENSS pin has
completed its soft-start ramp.
Additionally, a capacitor on the CDEL pin will set a delay for
the PGOOD signal. After the ENSS pin completes its soft-
start ramp, a 2μA current begins charging the CDEL
FN9151.5
February 13, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6420IRZ-TKR5207 | 制造商:Intersil Corporation 功能描述: |
| ISL6420IRZ-TKS2698 | 制造商:Intersil Corporation 功能描述:PB-FREE SYNCH BUCK PWM CONT. WITH 4.5V-16V INPUT,20LD 4X4 QF - Tape and Reel |
| ISL6421AER | 功能描述:IC REG SGL LNB CONTROL 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6421AER-T | 功能描述:IC REG SGL LNB CONTROL 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6421AERZ | 功能描述:电流型 PWM 控制器 SINGLE LNBP SUPPLY CONTROL VG 32LD MLFP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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