参数资料
型号: ISL6420IRZ-TK
厂商: Intersil
文件页数: 14/19页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20-QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 100%
电源电压: 4.5 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6420
capacitor to 2.5V. The capacitor will be quickly discharged
before PGOOD goes high. The programmable delay can be
used to sequence multiple converters or as a LOW-true
reset signal.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
V IN
ISL6420
UGATE
PHASE
Q1
L O
V OUT
FIGURE 12. PGOOD DELAY
If the voltage on the FB pin exceeds ±10% of the reference,
then PGOOD will go low after 3μs of noise filtering.
LGATE
GND
Q2
D2
C IN
C O
Over-Temperature Protection
The IC is protected against over temperature conditions.
When the junction temperature exceeds +150°C, the PWM
shuts off. Normal operation is resumed when the junction
temperature is cooled down to +130°C.
Shutdown
When ENSS pin is below 1V, the regulator is disabled with
the PWM output drivers tri-stated. When disabled, the IC
power will be reduced.
Under-Voltage
If the voltage on the FB pin is less than 15% of the reference
voltage for 8 consecutive PWM cycles, then the circuit enters
into soft-start hiccup mode. This mode is identical to the
overcurrent hiccup mode.
Overvoltage Protection
If the voltage on the FB pin exceeds the reference voltage by
15%, the lower gate driver is turned on continuously to
discharge the output voltage. If the overvoltage condition
continues for 32 consecutive PWM cycles, then the chip is
turned off with the gate drivers tri-stated. The voltage on the
FB pin will fall and reach the 15% undervoltage threshold.
After 8 clock cycles, the chip will enter soft-start hiccup
mode. This mode is identical to the overcurrent hiccup
mode.
14
RETURN
FIGURE 13. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 12 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 12 should be located as close
together as possible. Please note that the capacitors C IN
and C O each represent numerous physical capacitors.
Locate the ISL6420 within 3 inches of the MOSFETs, Q1 and
Q2. The circuit traces for the MOSFETs’ gate and source
connections from the ISL6420 must be sized to handle up to
1A peak current.
Figure 13 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the ENSS PIN and locate the capacitor, C ss
close to the ENSS pin because the internal current source is
only 30μA. Provide local V CC decoupling between VCC and
GND pins. Locate the capacitor, C BOOT as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
Figure 14 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V E/A ) is compared with the
FN9151.5
February 13, 2008
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