参数资料
| 型号： | ISL6424ERZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC REG DUAL LNBP TTL-INP 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 13 V ~ 18 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
ISL6424
Received Data ( I 2 C bus READ MODE)
The ISL6424 can provide to the master a copy of the system
register information via the I 2 C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6424 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
? Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6424.
? Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
the read-only bits OLF1, OLF2, and OTF convey diagnostic
information about the ISL6424.
Power-On I 2 C Interface Reset
interface will not respond to any I 2 C commands and the
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the Vcc rises
above UVLO, the POWER OK signal given to the I 2 C
interface block will be HIGH, the I 2 C interface becomes
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the Power-
On reset circuit. (I 2 C comes up with EN = 0; EN goes HIGH
at the same time as (or later than) all other I 2 C data for that
PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I 2 C interface address is
0001000, but, it is possible to choose between two different
addresses simply by setting this pin at one of the two fixed
voltage levels as shown in Table 8.
TABLE 6. ADDRESS PIN CHARACTERISTICS
The I 2 C interface built into the ISL6424 is automatically reset
at power-on. The I 2 C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
V ADDR
V ADDR -1
“0001000”
V ADDR -2
“0001001”
MINIMUM
0V
2.7V
TYPICAL
-
-
MAXIMUM
2V
5V
TABLE 7. READING SYSTEM REGISTERS
DCL
ISEL1/2
ENT1/2
LLC1/2
VSEL1/1
EN1/2
OTF2
OLF1/2
FUNCTION
These bits are read as they were after the last write operation.
0
1
0
1
T J ≤ 130°C, normal operation
T J > 150°C, power blocks disabled
I OUT < I MAX , normal operation
I OUT > I MAX , overload protection triggered
I 2 C Electrical Characteristics
TABLE 8. I 2 C SPECIFICATIONS
PARAMETER
TEST CONDITION
MINIMUM
TYPICAL
MAXIMUM
Input Logic High, VIH
Input Logic Low, VIL
Input Logic Current, IIL
SDA, SCL
SDA, SCL
SDA, SCL;
0.4V < V IN < 4.5V
0.7 x V DD
0.3 x V DD
10 μ A
SCL Clock Frequency
11
0
100kHz
400kHz
FN9175.3
September 13, 2005
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