参数资料
| 型号： | ISL6424ERZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC REG DUAL LNBP TTL-INP 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 13 V ~ 18 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
ISL6424
Typical Performance Curves
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
I OUT _max
0.00
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 1. OUTPUT CURRENT DERATING
NOTE: With both channels in simultaneous operation at rated output
Functional Pin Description
Functional Description
SYMBOL
SDA
SCL
VSW1, 2
FUNCTION
Bidirectional data from/to I 2 C bus.
Clock from I 2 C bus.
Input of the linear post-regulator.
The ISL6424 dual output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. Both supply and control voltage
outputs for two low-noise blocks (LNBs) are available
simultaneously in any output configuration. The device
PGND1, 2 Dedicated ground for the output gate driver of
respective PWM.
utilizes built-in DC/DC step-converters that, from a single
supply source ranging from 8V to 14V, generate the voltages
CS1, 2
SGND
AGND
TCAP1, 2
Current sense input; connect Rsc at this pin for
desired over current value for respective PWM.
Small signal ground for the IC.
Analog ground for the IC.
Capacitor for setting rise and fall time of the output of
that enable the linear post-regulators to work with a
minimum of dissipated power. An undervoltage lockout
circuit disables the circuit when VCC drops below a fixed
threshold (7.5V typ).
DiSEqC Encoding
LNB A and LNB B respectively. Use this capacitor
value 1μF or higher.
BYPASS Bypass capacitor for internal 5V.
DSQIN1, 2 When HIGH enables internal 22kHz modulation for
LNB A and LNA B respectively, Use this pin for tone
enable function for LNB A and LNB B.
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSEqC (EUTELSAT) standards.
No further adjustment is required. The 22kHz oscillator can be
controlled either by the I 2 C interface (ENT1/2 bit) or by a
dedicated pin (DSQIN1/2) that allows immediate DiSEqC data
encoding separately for each LNB. (Please see Note 1 at the
VCC
GATE1, 2
VO1, 2
ADDR
Main power supply to the chip.
These are the device outputs of PWM A and PWM B
respectively. These high current driver outputs are
capable of driving the gate of a power FET. These
outputs are actively held low when Vcc is below the
UVLO threshold.
Output voltage of LNB A and LNB B respectively.
Address pin to select two different addresses per
voltage level at this pin.
end of this section.) All the functions of this IC are controlled
via the I 2 C bus by writing to the system registers (SR1, SR2).
The same registers can be read back, and two bits will report
the diagnostic status. The internal oscillator operates the
converters at ten times the tone frequency. The device offers
full I 2 C compatible functionality, 3.3V or 5V, and up to 400kHz
operation.
If the Tone Enable (ENT1/2) bit is set LOW through I 2 C, then
COMP1, 2 Error amp outputs used for compensation.
FB1, 2 Feedback pins for respective PWMs
CPVOUT, Charge pump connections.
CPSWIN,
CPSWOUT
SEL18V1, 2 When connected HIGH, this pin will change the output
of the respective PWM to 18V.
7
the DSQIN1/2 terminal activates the internal tone signal,
modulating the dc output with a 0.3V, 22kHz, symmetrical
waveform. The presence of this signal usually gives the LNB
information about the band to be received.
Burst coding of the 22kHz tone can be accomplished due to
the fast response of the DSQIN1/2 input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
FN9175.3
September 13, 2005
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