参数资料
| 型号： | ISL6425ER-T |
| 厂商： | Intersil |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC REG DUAL LNBP TTL-INP 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 13 V ~ 18 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
ISL6425
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
SR1
0
0
0
0
0
0
0
0
0
0
0
0
SR2
1
DCL
X
X
X
X
X
X
X
X
X
1
0
X
-
X
ISEL1
X
X
X
X
X
X
X
0
1
X
X
X
-
X
ENT1
X
X
X
X
X
0
1
X
X
X
X
X
-
X
LLC1
0
0
0
1
1
X
X
X
X
X
X
X
-
X
VSEL1
0
0
1
0
1
X
X
X
X
X
X
X
EN2
0
EN1
X
1
1
1
1
1
1
1
1
1
1
0
OTF
X
OLF1
X
X
X
X
X
X
X
X
X
X
X
X
-
X
FUNCTION
SR1 is selected
Vout1 = 13V, Vboost1 = 13V + Vdrop
Vout1 = 18V, Vboost1 = 18V + Vdrop
Vout1 = 14V, Vboost1 = 14V + Vdrop
Vout1 = 19V, Vboost1 = 19V + Vdrop
22kHz tone is controlled by the DSQIN pin
22kHz tone is ON, the DSQIN input is disabled
Iout1 = 425mA max.
Iout1 = 775mA max.
Dynamic current limit NOT selected
Dynamic current limit selected
PWM and Linear for channel 1 disabled
FUNCTION
SR2 is selected; to read OTF flag.
NOTE: OTF is a “Read Only” bit and X indicates a “Don’t Care” condition for the function specified.
Received Data ( I 2 C Bus Read Mode)
The ISL6425 can provide to the master a copy of the System
Register information via the I 2 C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6425 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
? Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6425.
? Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6425.
TABLE 6. READING SYSTEM REGISTERS
Power-On I 2 C Interface Reset
The I 2 C interface built into the ISL6425 is automatically reset
at power-on. The I 2 C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I 2 C commands and the
system register SR is initialized to all zeros, thus keeping the
power blocks disabled.
DCL ISEL ENT LLC VSEL EN OTF OLF
FUNCTION
These bits are read as they were
0
Tj ≤ 130°C, Normal
after the last write operation.
10
1
0
1
operation
Tj > 150°C, Power
blocks disabled
Iout < Imax, Normal
operation
Iout > Imax, Overload
protection triggered
FN9176.1
February 8, 2005
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