参数资料
| 型号： | ISL6431CB-T |
| 厂商： | Intersil |
| 文件页数： | 7/10页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 8-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 340kHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
ISL6431
6. Check Gain against Error Amplifier ’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
F Z1 = ------------------------------------
F Z2 = -------------------------------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ----------------------
F P2 = ------------------------------------
1
2 π x R 2 x C 1
1
2 π x ( R 1 + R 3 ) x C 3
1
C 1 x C 2
C 1 + C 2
1
2 π x R 3 x C 3
High frequency capacitors initially supply the transient and
slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the
ESR (Effective Series Resistance) and voltage rating
Figure 6 shows an asymptotic plot of the DC-DC converter ’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Refer to the evaluation board application note (available
soon) for a complete reference design schematic and bill of
materials for a typical Residential Gateway application.
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor ’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
100
F Z1 F Z2
F P1
F P2
ripple requirements and minimize the converter ’s response
time to the load transient. The inductor value determines the
80
converter ’s ripple current and the ripple voltage is a function
60
OPEN LOOP
ERROR AMP GAIN
of the ripple current. The ripple voltage and current are
? V OUT = ? I x ESR
? I =
40
20
0
-20
-40
20LOG
(R 2 /R 1 )
MODULATOR
GAIN
20LOG
(V IN / D V OSC )
COMPENSATION
GAIN
CLOSED LOOP
GAIN
approximated by the following equations:
V IN - V OUT V OUT
x
Fs x L V IN
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter ’s response time to a load transient.
F ESR
-60
10
100
1K
F LC
10K 100K
FREQUENCY (Hz)
1M
10M
One of the parameters limiting the converter ’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
7
ISL6431 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
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相关代理商/技术参数 |
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| ISL6431IB | 制造商:Intersil Corporation 功能描述: |
| ISL6432CB | 制造商:Intersil Corporation 功能描述: |
| ISL6432CB-T | 功能描述:IC REG QD BCK/LINEAR 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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