参数资料
| 型号： | ISL6431CB-T |
| 厂商： | Intersil |
| 文件页数： | 8/10页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 8-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 340kHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
ISL6431
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
across the lower MOSFET clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not
adequately model power loss due the reverse-recovery of
t RISE =
L x I TRAN
V IN - V OUT
t FALL =
L x I TRAN
V OUT
the lower MOSFET’s body diode. The gate-charge losses
are dissipated by the ISL6431 and don't heat the
MOSFETs. However, large gate-charge increases the
where: I TRAN is the transient load current step, t RISE is the
response time to the application of load, and t FALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
switching interval, t SW which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient
temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Input Capacitor Selection
P UPPER = Io 2 x r DS(ON) x D +
1
2
Io x V IN x t SW x F S
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q 1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q 1 and the source of Q 2 .
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
P LOWER = Io 2 x r DS(ON) x (1 - D)
Where: D is the duty cycle = V OUT / V IN ,
t SW is the switch ON time, and
F S is the switching frequency.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors have to be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low V GS(ON) characteristics, as the low gate
threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the ISL6431.
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
+5V
D BOOT
1/2 the DC load current.
VCC
+ V D -
+5V
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
ISL6431
BOOT
C BOOT
Q1
regard to the capacitor surge current rating. These capacitors
UGATE
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
PHASE
NOTE:
V G-S ≈ V CC -V D
are surge current tested.
MOSFET Selection/Considerations
-
+
LGATE
Q2
NOTE:
The ISL6431 requires two N-Channel power MOSFETs for use
in a synchronous buck configuration. These should be selected
based upon r DS(ON) , gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only
the upper MOSFET has switching losses, since the lower
MOSFETs body diode or an external Schottky rectifier
8
V G-S ≈ V CC
GND
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V CC . The boot capacitor, C BOOT ,
develops a floating supply voltage referenced to the PHASE
pin. The supply is refreshed to a voltage of V CC less the boot
diode drop (V D ) each time the lower MOSFET, Q 2 , turns on.
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