参数资料
型号: ISL6505CB
厂商: Intersil
文件页数: 6/17页
文件大小: 0K
描述: IC MULTIPLE POWER CTRLR 20-SOIC
标准包装: 38
应用: 电源控制器/监控器
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 6mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC W
包装: 管件
ISL6505
Pinouts
ISL6505 (20 LEAD WIDE SOIC)
TOP VIEW
ISL6505 (5 X 5 QFN)
TOP VIEW
FB1
DR1
3V3DLSB
1
2
3
20 5VSB
19 VID_CT
18 VID_PG
3V3DL
1V2VID
3V3
4
5
6
17 SS
16 LAN
15 5VDL
3V3DL
1V2VID
1
2
20
19
18
17
16
15 VID_PG
14 SS
5V
7
14 5VDLSB
EN5
S3
8
9
13 DLA
12 FAULT
3V3
5V
3
4
13 LAN
12 5VDL
S5 10
11 GND
EN5
5
11 5VDLSB
6
7
8
9
10
NOTE: The QFN bottom pad is electrically connected to the IC
substrate, at GND potential. It can be left unconnected, or connected
to GND; do NOT connect to another potential.
Functional Pin Description (Pin numbers for SOIC and QFN)
3V3 (Pin 6 SOIC; Pin 3 QFN)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 1V2VID pin, and is monitored for
power quality.
5V (Pin 7 SOIC; Pin 4 QFN)
Connect this pin to the ATX 5V output. This pin is only
monitored for power quality.
5VSB (Pin 20 SOIC; Pin 17 QFN)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5V SB output. This pin
provides all the chip’s bias as well as the base current for Q2
(see typical application diagram). The voltage at this pin is
monitored for power-on reset (POR) purposes.
GND (Pin 11 SOIC; Pin 8 QFN)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
S3 and S5 (Pins 9, 10 SOIC; Pins 6, 7 QFN)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50μA (typical) current source pull-
ups to 5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2 μ s (typically). Additional
circuitry blocks illegal state transitions (such as S4/S5 to S3),
but does allow S3 to S4/S5. Connect S3 and S5
respectively to the computer system’s SLP_S3 and SLP_S5
signals.
6
EN5 (Pin 8 SOIC; Pin 5 QFN)
This digital input selects whether the 5VDL output stays up
or shuts down during the S5 Sleep Mode. It has a 10μA
typical pull-up current source. A logic high (5V) or open will
keep the 5VDL on during S5; a logic low (GND) will shut it off
during S5. NOTE: This pin should be tied low or high (or
open) on the board; it was not designed to be changed
during normal operation.
LAN (Pin 16 SOIC; Pin 13 QFN)
This digital input selects between two modes for the V OUT1
regulator. It has a 10μA pull-up current source. A logic high
(5V) or open selects the 10/100 LAN mode, where V OUT1
stays on all of the time (active and sleep modes). A logic low
(GND) selects the Gigabit Ethernet mode, where V OUT1 is
only on during active (S0, S1) modes. Note that this
selection is independent of the voltage selection of V OUT1
(which is determined by the external resistor divider). NOTE:
This pin should be tied low or high (or open) on the board; it
was not designed to be changed during normal operation.
FAULT (Pin 12 SOIC; Pin 9 QFN)
This digital output pin is used to report the fault condition by
being pulled to 5VSB (pulled to GND if no fault). It is a
CMOS digital output; an external pull-down resistor is NOT
required. In case of an undervoltage on any of the controlled
outputs, on any of the monitored ATX voltages (3V3 or 5V;
not 12V), or in case of an overtemperature event, this pin is
used to report the fault condition.
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