参数资料
型号: ISL6505CB
厂商: Intersil
文件页数: 9/17页
文件大小: 0K
描述: IC MULTIPLE POWER CTRLR 20-SOIC
标准包装: 38
应用: 电源控制器/监控器
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 6mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC W
包装: 管件
ISL6505
Soft-Start into Sleep States (S3, S4/S5)
The 5V SB POR function initiates the soft-start sequence. An
internal 10μA current source charges an external capacitor.
The error amplifiers’ reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.4V to 3.0V, the input clamp
allows a rapid and controlled output voltage rise.
Figures 7 (EN5 = low) and 8 (EN5 = high) show the soft-start
sequence for the typical application start-up into a sleep
state. At time T0 5V SB (bias) is applied to the circuit. At time
T1, the 5V SB surpasses POR level. An internal fast charge
0V
5V SB
(1V/DIV)
SOFT-START
(1V/DIV)
V OUT4 (5V DUAL )
circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10 μ A current source continues
V OUT3 (3.3V DUAL /3.3V SB )
the charging.
OUTPUT
VOLTAGES
(1V/DIV)
V OUT1
5V SB
(1V/DIV)
SOFT-START
0V
T0
T1 T2
T3
TIME
T4
T5
V OUT2
(1.2V VID )
0V
(1V/DIV)
V OUT3 (3.3V DUAL /3.3V SB )
V OUT4 (5V DUAL ) if S3
FIGURE 8. SOFT-START INTERVAL IN A SLEEP STATE;
EN5 = 5V/OPEN; LAN = 5V/OPEN
The soft-start capacitor voltage reaches approximately 1.4V
at time T2, at which point the 3.3V DUAL /3.3V SB and V OUT1
error amplifiers’ reference inputs start their transition,
resulting in the output voltages ramping up proportionally.
The ramp-up continues until time T3 when the two voltages
reach the set value. As the soft-start capacitor voltage
reaches approximately 3.0V, the undervoltage monitoring
circuit of this output is activated and the soft-start capacitor
OUTPUT
VOLTAGES
(1V/DIV)
V OUT1
is quickly discharged to approximately 1.4V. Following the
3ms (typical) time-out between T3 and T4, the soft-start
capacitor commences a second ramp-up designed to
0V
V OUT4 (5V DUAL ) if S5
V OUT2
(1.2V VID )
smoothly bring up the remainder of the voltages required by
the system. At time T5, voltages are within regulation limits,
and as the SS voltage reaches 3.0V, all the remaining UV
T0 T1 T2
T3
TIME
T4
T5
monitors are activated and the SS capacitor is quickly
discharged to 1.4V, where it remains until the next transition.
FIGURE 7. SOFT-START INTERVAL IN A SLEEP STATE; EN5
= GND; LAN = 5V/OPEN
As the 1.2V VID output is only on while in an active state, it
does not come up, but rather waits until the main ATX
outputs come up within regulation limits.
Note that in Figures 7 and 8, LAN = 5V/open. If the LAN pin
is connected to GND instead, then the V OUT1 output does
not turn on at all in either sleep mode (S3 or S4/S5).
Soft-Start into Active States (S0, S1)
If both S3 and S5 are logic high at the time the 5V SB is
applied, the ISL6505 will assume active state wake-up and
keep off the required outputs until some time (typically 50ms)
after the monitored main ATX outputs (3.3V and 5V; 12V is
not monitored here) exceed the set thresholds. This time-out
feature is necessary in order to ensure the main ATX outputs
are stabilized. The time-out also assures smooth transitions
from sleep into active when sleep states are being
9
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