参数资料
| 型号： | ISL6535CRZ |
| 厂商： | Intersil |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
ISL6535
C 1 = -----------------------------------------------
2 π ? R 2 ? C 1 ? F CE – 1
F Z1 F Z2
F P1
F P2
1
2 π ? R 2 ? 0.5 ? F LC
3. Calculate C 2 such that F P1 is placed at F CE .
C 1
C 2 = --------------------------------------------------------
(EQ. 10)
(EQ. 11)
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below f SW (typically, 0.3 to 1.0
times f SW ). f SW represents the switching frequency of the
20 log ? ? ? ?
--------
MAX ? IN
OSC
regulator. Change the numerical factor (0.7) below to
reflect desired placement of this pole. Placement of F P2
lower in frequency helps reduce the gain of the
compensation network at high frequency, in turn reducing
0
R2
R1
D V
20 log ----------------------------------
V
G FB
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
G CL
R 3 = --------------------
f SW
R 1
----------- – 1
F LC
(EQ. 12)
LOG
F LC
F CE
F 0
G MOD
FREQUENCY
C 3 = -----------------------------------------------
D MAX ? V IN 1 + s ( f ) ? ESR ? C
G MOD ( f ) = ------------------------------- ? -----------------------------------------------------------------------------------------------------------
G FB ( f ) = ---------------------------------------------------- ?
1 + s ( f ) ? ( R 1 + R 3 ) ? C 3
( 1 + s ( f ) ? R 3 ? C 3 ) ? ? 1 + s ( f ) ? R 2 ? ? ? ?
? ? C 1 ? C 2 ? ?
1
2 π ? R 3 ? 0.7 ? f SW
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier ’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G MOD ), feedback
compensation (G FB ) and closed-loop response (G CL ):
V OSC 1 + s ( f ) ? ( ESR + DCR ) ? C + s ( f ) ? L ? C
1 + s ( f ) ? R 2 ? C 1
s ( f ) ? R 1 ? ( C 1 + C 2 )
-------------------------------------------------------------------------------------------------------------------------
---------------------
? ? C 1 + C 2 ? ?
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, f SW .
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
G CL ( f ) = G MOD ( f ) ? G FB ( f )
where , s ( f ) = 2 π ? f ? j
(EQ. 13)
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
COMPENSATION BREAK FREQUENCY EQUATIONS
capacitors and careful layout.
F Z1 = -------------------------------
F Z2 = -------------------------------------------------
F P1 = ---------------------------------------------
2 π ? R 2 ? ---------------------
F P2 = -------------------------------
1
2 π ? R 2 ? C 1
1
2 π ? ( R 1 + R 3 ) ? C 3
1
C 1 ? C 2
C 1 + C 2
1
2 π ? R 3 ? C 3
(EQ. 14)
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previously mentioned guidelines
should yield a compensation gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F P2 against the
capabilities of the error amplifier. The closed loop gain, G CL , is
constructed on the log-log graph of Figure 8 by adding the
modulator gain, G MOD (in dB), to the feedback
compensation gain, G FB (in dB). This is equivalent to
10
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor ’s ESR will determine the output ripple
FN9255.1
May 5, 2008
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| ISL6535CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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