参数资料
型号: ISL6535CRZ
厂商: Intersil
文件页数: 8/14页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 100%
电源电压: 10.8 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
ISL6535
R OCSET = ----------------------------------------------------------------
? I
+ ----- ? ? r
? OC_SOURCE 2 ?
I HSOC ? N U
V IN - V OUT V OUT
f SW ? L OUT
The OCP trip point varies mainly due to MOSFET r DS(ON)
variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the R OCSET
resistor from the following equations with:
1. The maximum r DS(ON) at the highest junction
temperature
2. The minimum I OCSET from the specification table
Determine the overcurrent trip point greater than the
maximum output continuous current at maximum inductor
ripple current.
SIMPLE OCP EQUATION
I OC_SOURCE ? r DS ( ON )
200 μ A
DETAILED OCP EQUATION
Δ I
DS ( ON )
R OCSET = ----------------------------------------------------------------------------------
N U = NUMBER OF HIGH SIDE MOSFETs
Δ I = -------------------------------- ? ----------------
V IN
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
A multi-layer printed circuit board is recommended. Figure 5
shows the critical components of the converter. Note that
capacitors C IN and C OUT could each represent numerous
physical capacitors. Dedicate one solid layer (usually a middle
layer of the PC board) for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. Keep the
metal runs from the PHASE terminals to the output inductor
short. The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the
remaining printed circuit layers for small signal wiring.
f SW = Regulator Switching Frequency
High Speed MOSFET Gate Driver
(EQ. 6)
VCC
+12V
C BP_PVCC
PVCC
ISL6535
C BP_VCC
VIN
UGATE
BOOT
Q 1
C IN
Reference Input
PHASE
C IN
L OUT
V OUT
The REFIN pin allows the user to bypass the internal 0.597V
reference with an external reference. If REFIN is NOT above
C OUT
~2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. When not
using the external reference option, the REFIN pin should be
LGATE
SS
Q 2
left floating. An internal 6 μ A pull-up keeps this REFIN pin
GND
PGND
C SS
above 2.2V in this situation.
Internal Reference and System Accuracy
The Internal Reference is set to 0.597V. The total DC system
accuracy of the system is to be within 1.0% over commercial
temperature range and 1.5% over the industrial temperature
range. System Accuracy includes Error Amplifier offset, and
KEY
TRACE SIZED FOR 3A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
ISLAND ON POWER PLANE LAYER
Reference Error. The use of REFIN may add up to 3mV of
offset error into the system (as the Error Amplifier offset is
trimmed out via the internal System reference).
8
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
FN9255.1
May 5, 2008
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