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| 型号： | ISL6537A |
| 厂商： | Intersil Corporation |
| 英文描述： | ACPI Regulator/Controller for Dual Channel DDR Memory Systems |
| 中文描述： | ACPI的稳压器/双通道DDR内存控制器系统 |
| 文件页数： | 13/15页 |
| 文件大小： | 488K |
| 代理商： | ISL6537A |
7
FN9143.3
FB3 (Pin 18)
Connect the output of the DAC linear regulator to this pin
through a properly sized resistor divider. The voltage at this
pin is regulated to 0.8V.
DRIVE3 (Pin 10)
This pin provides the gate voltage for the DAC linear
regulator pass transistor. Connect this pin to the gate
terminal of an external N-Channel MOSFET transistor.
VIDPGD (Pin 12)
The VIDPGD pin is an open-drain logic output that changes
to a logic low if the VTT_GMCH/CPU linear regulator is out of
regulation in S0/S1/S2 state. VIDPGD will always be low in
any state other than S0/S1/S2.
SLP_S5# (Pin 23)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 2)
This pin accepts the SLP_S3# sleep state signal.
Functional Description
Overview
The ISL6537A provides complete control, drive, protection
and ACPI compliance for regulator powering DDR memory
systems and the GMCH core and GMCH/CPU termination
rails. It is primarily designed for computer applications
powered from an ATX power supply.
A 250kHz Synchronous Buck Regulator with a precision
0.8V reference provides the proper Core voltage to the
system memory of the computer. An internal LDO regulator
with the ability to both sink and source current and an
externally available buffered reference that tracks the VDDQ
output by 50% provides the VTT termination voltage.
A second 250kHz PWM Buck regulator, which requires an
external MOSFET driver, provides the GMCH core voltage.
This PWM regulator is 180° out of phase with the PWM
regulator used for the Memory core. Two additional LDO
controllers are included, one for the regulation of the
GMCH/CPU termination rail and the second for the DAC.
ACPI compliance is realized through the SLP_S3 and
SLP_S5 sleep signals and through monitoring of the 12V
ATX bus.
Initialization
The ISL6537A automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors
the bias voltage at the 5VSBY and P12V pins. The POR
function initiates soft-start operation after the bias supply
voltages exceed their POR thresholds.
ACPI State Transitions
Figure 1 shows how the individual regulators are controlled
during all state transitions. All references to timing in this
section are in reference to Figure 1.
Cold Start (S4/S5 to S0 Transition)
At the onset of a mechanical start, time t0 in Figure 1, the
ISL6537A receives its bias voltage from the 5V Standby bus
(5VSBY). Once the 5VSBY rail has exceeded the POR
threshold, the ISL6537A will remain in an internal S5 state
until both the SLP_S3 and SLP_S5 signal have transitioned
high and the 12V POR threshold has been exceeded by the
+12V rail from the ATX, which occurs at time t1.
Once all of these conditions are met, the PWM error
amplifiers will first be reset by internally shorting the COMP
pins to the respective FB pins. This reset lasts for three soft-
start cycles, which is typically 24ms (one soft-start cycle is
typically 8.2ms). The digital soft-start sequence will then
begin. Each regulator is enabled and soft-started according
to a preset sequence.
At time t2, the 3 soft-start cycle reset has ended and the
VDDQ_DDR rail is digitally soft-started.
The digital soft-start for both PWM regulators is accomplished
by clamping the error amplifier reference input to a level
proportional to the internal digital soft-start voltage. As the soft-
start voltage slews up, the PWM comparator generates PHASE
pulses of increasing width that charge the output capacitor(s).
This method provides a rapid and controlled output voltage rise.
The linear regulators, with the exception of the internal
VTT_DDR LDO, are soft-started in a similar manner. The
error amplifier reference is clamped to the internal digital
soft-start voltage. As the soft-start voltage ramps up, the
respective DRIVE pin voltages increase, thus enhancing the
N-MOSFETs and charging the output capacitors in a
controlled manner.
At time t3, the VDDQ_DDR rail is in regulation and the
VGMCH rail is soft-started. At time t4, the VGMCH rail is in
regulation and the VTT_GMCH/CPU and the DAC linear
regulators are soft-started. At time t5, the VTT_GMCH/CPU
rail and DAC rails are in regulation and the VTT_DDR internal
regulator is soft-started.
The VTT_DDR LDO soft-starts in a manner unlike the other
regulators. When the VTT_DDR regulator is disabled, the
reference is internally shorted to the VTT_DDR output. This
allows the termination voltage to float during the S3 sleep
state. When the ISL6537A enables the VTT_DDR regulator
or enters S0 state from a sleep state, this short is released
and the internal divide down resistors which set the
VTT_DDR voltage to 50% of VDDQ_DDR will provide a
controlled voltage rise on the capacitor that is tied to the
VREF_IN pin. The voltage on this capacitor is the reference
for the VTT_DDR regulator and the output will track it as it
settles to 50% of the VDDQ voltage. The combination of the
ISL6537A
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