参数资料
型号: ISL6539CA
厂商: Intersil
文件页数: 5/20页
文件大小: 0K
描述: IC CTRLR DDR DRAM, SDRAM 28QSOP
标准包装: 48
应用: 控制器,DDR DRAM,SDRAM
输入电压: 3.3 V ~ 18 V
输出数: 2
输出电压: 0.9 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.154",3.90mm 宽)
供应商设备封装: 28-SSOP/QSOP
包装: 管件
ISL6539
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONVERTERS
Load Regulation
0.0mA < IVOUT1 <5.0A; 5.0V < VIN <15.0V
-2.0
-
+2.0
%
VSEN Pin Bias Current
Minimum Duty Cycle
Maximum Duty Cycle
Undervoltage Shut-Down Level
Overvoltage Protection
IVSEN
DMIN
DMAX
VUVL
VOVP1
(Note 3)
Fraction of the set point; ~2μs noise filter
Fraction of the set point; ~2μs noise filter
-
-
-
70
110
80
4
87
75
115
-
-
-
80
-
nA
%
%
%
%
GATE DRIVERS
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
R2UGPUP VCC = 5V
R2UGPDN VCC = 5V
-
-
4
2.3
8
4
Ω
Ω
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
R2LGPUP
R2LGPDN
VCC = 5V
VCC = 5V
-
-
4
1.1
8
3
Ω
Ω
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
Power Good Higher Threshold
PGOODx Leakage Current
PGOODx Voltage Low
ISEN Sourcing Current
OCSET Sourcing Current Range
EN - Low (Off)
EN - High (On)
DDR - Low (Off)
DDR - High (On)
DDR REF Output Voltage
VPG -
VPG+
IPGLKG
VPGOOD
VDDREF
Fraction of the set point; ~3μs noise filter
Fraction of the set point; ~3μs noise filter.
VPULLUP = 5.5V
IPGOOD = -4mA
(Note 3)
DDR = 1, IREF = 0...10mA
84
110
-
-
-
2
-
2.0
-
3
0.99*
89
115
-
0.5
-
-
-
-
-
-
VOC2
92
120
1
1
260
20
0.8
-
0.8
-
1.01*
%
%
μA
V
μA
μA
V
V
V
V
V
VOC2
VOC2
DDR REF Output Current
IDDREF
DDR = 1 (Note 3)
-
10
12
mA
NOTES:
3. Limits should be considered typical and are not production tested.
Functional Pin Description
GND (Pin 1, 9, 20)
Signal ground for the IC. All three ground pins must be
connected to ground for proper IC operation. Connect to the
ground plane through a path as low in inductance as
possible.
LGATE1, LGATE2 (Pin 2, 27)
Connect these pins to the gates of the corresponding lower
MOSFETs. These pins provide the PWM-controlled gate
drive for the lower MOSFETs.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters. These pins must
5
be connected to the ground plane through a path as low in
inductance as possible.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter ’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
Connect these pins to the gates of the corresponding upper
MOSFETs. These pins provide the PWM-controlled gate
drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect these pins to the junction of the bootstrap
FN9144.6
April 29, 2010
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