参数资料
| 型号： | ISL6548ACRZA-T |
| 厂商： | Intersil |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG/CTLR ACPI DUAL DDR 28QFN |
| 标准包装： | 1 |
| 应用： | 存储器，DDR/DDR2 稳压器 |
| 电流 - 电源： | 7mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（6x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6548ACRZA-TDKR |
ISL6548A
allows the termination voltage to float during the S3 sleep
state. When the ISL6548A enables the V TT_DDR regulator
or enters S0 state from a sleep state, this short is released
and the internal divide down resistors which set the
V TT_DDR voltage to 50% of V DDQ_DDR will provide a
controlled voltage rise on the capacitor that is tied to the
VREF_IN pin. The voltage on this capacitor is the reference
for the V TT_DDR regulator and the output will track it as it
settles to 50% of the V DDQ voltage. The combination of the
internal resistors and the V REF_IN capacitor will determine
the rise time of the V TT_DDR regulator (see the Functional
Pin Description section for proper sizing of the VREF_IN
capacitor).
At time t 6 , a full soft-start cycle has passed from the time that
the V TT_DDR regulator was enabled. At this time the
VIDPGD comparator is enabled. Once enabled if the
V TT_GMCH/CPU output is within regulation, the VIDPGD pin
will be forced to a high impedance state.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6548A will disable all the regulators except for the V DDQ
regulator, which is continually supplied by the 5VDUAL rail.
VIDPGD will also transition LOW. When V TT is disabled, the
internal reference for the V TT regulator is internally shorted
to the V TT rail. This allows the V TT rail to float. When
floating, the voltage on the V TT rail will depend on the
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V TT rail may not bleed down to
0V. Figure 1 shows how the individual regulators are
affected by the S3 state at time t 7 .
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6548A will initiate the soft-start sequence. This sequence
is very similar to the mechanical start soft-start sequencing.
The transition from S3 to S0 is represented in Figure 1
between times t 8 and t 14 .
At time t 8 , the SLP_S3 signal transitions HIGH. This enables
the ATX, which brings up the 12V rail. At time t 9 , the 12V rail
has exceeded the POR threshold and the ISL6548A enters a
reset mode that lasts for 3 soft-start cycles. At time t 10 , the 3
soft-start cycle reset is ended and the individual regulators
are enabled and soft-started in the same sequence as the
mechanical cold start sequence, with the exception that the
V DDQ regulator is already enabled and in regulation.
Active to Shutdown (S0 to S5 Transition)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6548A IC disables all
regulators and forces the VIDPGD pin LOW. This transition
is represented on Figure 1 at time t 15 .
10
Fault Protection
The ISL6548A monitors the V DDQ regulator for under and
overvoltage events. The V DDQ regulator also has overcurrent
protection. The internal V TT_DDR LDO regulator is monitored
for under and overvoltage events. All other regulators, with the
exception of the ICH7 LDO, are monitored for undervoltage
events.
An overvoltage event on either the V DDQ or V TT_DDR
regulator will cause an immediate shutdown of all regulators.
This can only be cleared by toggling the SLP_S5 signal such
that the system enters the S5 sleep state and then
transitions back to the active, S0, state.
If a regulator experiences any other fault condition (an
undervoltage or an overcurrent on V DDQ ), then that regulator,
and only that regulator, will be disabled and an internal fault
counter will be incremented by 1. If the disabled regulator is
used as the input for another regulator, then that cascoded
regulator will also experience a fault condition due to a loss of
input. The cascoded regulator will be disabled and the fault
counter incremented by 1.
At every fault occurrence, the internal fault counter is
incremented by 1 and an internal Fault Reset Counter is
cleared to zero. The Fault Reset Counter will increment once
for every clock cycle (1 clock cycle is typically 1/250kHz, or
4 μ s). If the Fault Reset Counter reaches a count of 16384
before another fault occurs, then the Fault Counter is
cleared to 0. If a fault occurs prior to the Fault Reset Counter
reaching a count of 16384, then the Fault Reset Counter is
set back to zero.
The ISL6548A will immediately shut down when the Fault
Counter reaches a count of 4 when the system is restarting
from an S5 state into the active, or S0, state. The ISL6548A
will immediately shut down when the Fault Counter reaches
a count of 5 at any other time.
The 16384 counts that are required to reset the Fault Reset
Counter represent 8 soft-start cycles, as one soft-start cycle is
2048 clock cycles. This allows the ISL6548A to attempt at least
one full soft-start sequence to restart the faulted regulators.
When attempting to restart a faulted regulator, the ISL6548A
will follow the preset start up sequencing. If a regulator is
already in regulation, then it will not be affected by the start
up sequencing.
V DDQ Overcurrent Protection
The overcurrent function protects the switching converter from
a shorted output by using the upper MOSFET on-resistance,
r DS(ON) , to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R OCSET )
programs the overcurrent trip level (see Typical Application
FN9189.2
January 3, 2006
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6548CRZA | IC REG/CTRLR ACPI DUAL DDR 28QFN |
| ISL6551IR-T | IC REG CTRLR FLYBACK PWM 28-QFN |
| ISL6552CR-T | IC REG CTRLR BUCK PWM 20-QFN |
| ISL6553CB-T | IC REG CTRLR BUCK PWM 16-SOIC |
| ISL6554CB-T | IC PWM CORE VOLTAGE REG 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6548CRZA | 功能描述:电压模式 PWM 控制器 W/ANNEAL 4-IN-1G FOR DDR/I915/925 RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6548CRZA-T | 功能描述:电压模式 PWM 控制器 W/ANNEAL 4-IN-1G FOR DDR/I915/925 RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6549CA | 功能描述:IC REG DL BCK/LINEAR 16-QSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| ISL6549CA-T | 功能描述:IC REG DL BCK/LINEAR 16-QSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| ISL6549CAZA | 功能描述:IC REG DL BCK/LINEAR 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
发布紧急采购，3分钟左右您将得到回复。