参数资料
| 型号： | ISL6548ACRZA-T |
| 厂商： | Intersil |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC REG/CTLR ACPI DUAL DDR 28QFN |
| 标准包装： | 1 |
| 应用： | 存储器，DDR/DDR2 稳压器 |
| 电流 - 电源： | 7mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（6x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6548ACRZA-TDKR |
ISL6548A
DRIVE2_U (Pin 10)
This pin provides the gate voltage for the V TT_GMCH/CPU
linear regulator upper pass transistor. Connect this pin to the
gate terminal of an external N-Channel MOSFET transistor.
DRIVE2_L (Pin 13)
This pin provides the gate voltage for the V TT_GMCH/CPU
linear regulator lower pass transistor. Connect this pin to the
gate terminal of an external N-Channel MOSFET transistor.
FB3 (Pin 20)
Connect the output of the ICH7 linear regulator to this pin
through a properly sized resistor divider. The voltage at this
pin is regulated to 0.8V.
DRIVE3 (Pin 21)
This pin provides the gate voltage for the ICH7 linear
regulator pass transistor. Connect this pin to the gate
terminal of an external N-Channel MOSFET transistor.
VIDPGD (Pin 12)
The VIDPGD pin is an open-drain logic output that changes
to a logic low if the V TT_GMCH/CPU linear regulator is out of
regulation in S0/S1/S2 state. VIDPGD will always be low in
any state other than S0/S1/S2.
SLP_S5# (Pin 23)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 2)
This pin accepts the SLP_S3# sleep state signal.
Functional Description
Overview
The ISL6548A provides complete control, drive, protection
and ACPI compliance for a regulator powering DDR memory
systems and the GMCH core and GMCH/CPU termination
rails. It is primarily designed for computer applications
powered from an ATX power supply.
A 250kHz Synchronous Buck Regulator with a precision
0.8V reference provides the proper Core voltage to the
system memory of the computer. An internal LDO regulator,
with the ability to both sink and source current, tracks the
V DDQ output by 50% and provides the V TT termination
voltage.
A second 250kHz PWM Buck regulator, which requires an
external MOSFET driver, provides the GMCH core voltage.
This PWM regulator is 180° out of phase with the PWM
regulator used for the Memory core. Two additional LDO
controllers are included, one for the regulation of the
GMCH/CPU termination rail and the second for the ICH7
LDO.
ACPI compliance is realized through the SLP_S3 and
SLP_S5 sleep signals and through monitoring of the 12V
ATX bus.
8
Initialization
The ISL6548A automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors
the bias voltage at the 5VSBY and P12V pins. The POR
function initiates soft-start operation after the bias supply
voltages exceed their POR thresholds.
ACPI State Transitions
Figure 1 shows how the individual regulators are controlled
during all state transitions. All references to timing in this
section are in reference to Figure 1.
Cold Start (S4/S5 to S0 Transition)
At the onset of a mechanical start, time t 0 in Figure 1, the
ISL6548A receives its bias voltage from the 5V Standby bus
(5VSBY). Once the 5VSBY rail has exceeded the POR
threshold, the ISL6548A will remain in an internal S5 state
until both the SLP_S3 and SLP_S5 signal have transitioned
high and the 12V POR threshold has been exceeded by the
+12V rail from the ATX, which occurs at time t 1 .
Once all of these conditions are met, the PWM error
amplifiers will first be reset by internally shorting the COMP
pins to the respective FB pins. This reset lasts for three soft-
start cycles, which is typically 24ms (one soft-start cycle is
typically 8.2ms). The digital soft-start sequence will then
begin. Each regulator is enabled and soft-started according
to a preset sequence.
At time t 2 , the 3 soft-start cycle reset has ended and the
V DDQ_DDR rail is digitally soft-started.
The digital soft-start for both PWM regulators is accomplished
by clamping the error amplifier reference input to a level
proportional to the internal digital soft-start voltage. As the soft-
start voltage slews up, the PWM comparator generates PHASE
pulses of increasing width that charge the output capacitor(s).
This method provides a rapid and controlled output voltage rise.
The linear regulators, with the exception of the internal
V TT_DDR LDO, are soft-started in a similar manner. The
error amplifier is reference is clamped to the internal digital
soft-start voltage. As the soft-start voltage ramps up, the
respective DRIVE pin voltages increase, thus enhancing the
N-MOSFETs and charging the output capacitors in a
controlled manner.
At time t 3 , the V DDQ_DDR rail is in regulation and the
V GMCH rail is soft-started. At time t 4 , the V GMCH rail is in
regulation and the V TT_GMCH/CPU and the ICH7 linear
regulators are soft-started. At time t 5 , the V TT_GMCH/CPU
rail and ICH7 rails are in regulation and the V TT_DDR
internal regulator is soft-started.
The V TT_DDR LDO soft-starts in a manner unlike the other
regulators. When the V TT_DDR regulator is disabled, the
reference is internally shorted to the V TT_DDR output. This
FN9189.2
January 3, 2006
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6548CRZA | IC REG/CTRLR ACPI DUAL DDR 28QFN |
| ISL6551IR-T | IC REG CTRLR FLYBACK PWM 28-QFN |
| ISL6552CR-T | IC REG CTRLR BUCK PWM 20-QFN |
| ISL6553CB-T | IC REG CTRLR BUCK PWM 16-SOIC |
| ISL6554CB-T | IC PWM CORE VOLTAGE REG 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6548CRZA | 功能描述:电压模式 PWM 控制器 W/ANNEAL 4-IN-1G FOR DDR/I915/925 RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6548CRZA-T | 功能描述:电压模式 PWM 控制器 W/ANNEAL 4-IN-1G FOR DDR/I915/925 RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6549CA | 功能描述:IC REG DL BCK/LINEAR 16-QSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| ISL6549CA-T | 功能描述:IC REG DL BCK/LINEAR 16-QSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| ISL6549CAZA | 功能描述:IC REG DL BCK/LINEAR 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
发布紧急采购，3分钟左右您将得到回复。