参数资料
型号: ISL6556ACR-T
厂商: Intersil
文件页数: 14/25页
文件大小: 0K
描述: IC CTRLR MULTIPHASE VRM10 32-QFN
标准包装: 6,000
应用: 控制器,Intel VR10X
输入电压: 3 V ~ 12 V
输出数: 4
输出电压: 0.84 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
ISL6556A
Load-Line Regulation
For Negative Offset (connect R OFS to GND):
R OFS = ------------------------------
Some microprocessor manufacturers require a precisely-
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can be level in the direction that works to
control the voltage spike coincident with fast load current
demand changes.
0.5 × R REF
V OFFSET
FB
(EQ. 8)
The magnitude of the spike is dictated by the ESR and ESL
DAC
DYNAMIC
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 5, a current proportional to the average
current in all active channels, I AVG , flows from FB through a
load-line regulation resistor, R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
R REF
REF
VCC
or
GND
VID D/A
E/A
creating an output voltage droop with a steady-state value
defined as:
R OFS
+
-
+
2.0V
V DROOP = I AVG R FB
(EQ. 5)
OFS
ISL6556ACB
-
0.5V
GND
VCC
In most cases, each channel uses the same R ISEN value to
sense current. A more complete expression for V DROOP is
derived by combining Equations 4 and 5.
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6556ACB (28-LEAD SOIC)
V DROOP = ------------- ---------------------- R FB
R ISEN
I OUT r DS ( ON )
N
(EQ. 6)
FB
Output-Voltage Offset Programming
The ISL6556A allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
DYNAMIC
DAC
OFS and VCC, the voltage across it is regulated to 2.0V.
This causes a proportional current (I OFS ) to flow into OFS. If
VID D/A
R REF
R OFS is connected to ground, the voltage across it is
regulated to 0.5V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R REF ) is equal to the desired offset voltage.
These functions are shown in Figures 6 and 7.
As evident in Figure 7, the OFSOUT pin must be connected
to the REF pin for this current injection to function in
ISL6556ACR. The current flowing through R REF creates an
offset at the REF pin, which is ultimately duplicated at the
E/A
REF
OFSOUT
VCC
or
GND
output of the regulator.
Once the desired output offset voltage has been determined,
2.0V
-
+
+
R OFS
V OFFSET
-
use the following formulae to set R OFS :
For Positive Offset (connect R OFS to VCC):
2 × R REF
R OFS = --------------------------
14
(EQ. 7)
0.5V
OFS
ISL6556ACR
VCC GND
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6556ACR (32-LEAD QFN)
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