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参数资料
| 型号： | ISL6559EVAL2 |
| 厂商： | Intersil |
| 文件页数： | 2/12页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD 2 ISL6559 |
| 标准包装： | 1 |
| 主要目的： | 特殊用途 DC/DC，VRM 电源 |
| 输出及类型： | 1，非隔离 |
| 功率 - 输出： | 67.6W |
| 输出电压： | 1.3V |
| 电流 - 输出： | 52A |
| 输入电压： | 5V，12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 250kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | HIP6601，ISL6559 |
Application Note 1137
number of active phases in the converter and is preset for
3-phase operation. JP2 is set with PHASE 3 in the ON
position. Before connecting the power supplies to the board,
place switches SW1 and SW2 in the OFF position.
Input Power Connections
Two ATX supply connections are provided on the
ISL6559EVAL2 board. The main ATX power connector
mates with the 20-pin header, J1, labeled ATX. The 12V
AUX power connector mates with a 4-pin header, J2, labeled
ATX12V. Insure both connections are secure and SW1 and
SW2 are in the OFF position before switching on the ATX
supply.
Three female-banana jacks are provided for connection of
bench-top supplies. Connect the +12V terminal to J3, +5V
terminal to J4, and the common ground to terminal J5. Turn
on the +5V supply first to energize the ENABLE and power
good circuitry, then turn on the +12V supply.
Once power is applied to the board, the PGOOD LED
indicator will begin to illuminate red. With SW1 in the OFF
position, the ENABLE input of the ISL6559 is held low and
the startup sequence is inhibited.
On-Board Load Transient Generator
Most bench-top electronic loads are not capable of
producing the current slew rates required to emulate modern
microprocessors. For this reason, a discrete transient load
generator is provided on the evaluation board, see Figure 1.
The generator produces a load pulse of 112 μ s in duration
with a period of 14.5ms. The pulse magnitude is
approximately 20A, with rise and fall slew rates of
approximately 30A/ μ s as configured. The short load current
pulse and long duty cycle is required to limit the power
dissipation in the load resistors (R34-R38) and MOSFETs
(Q7, Q8). To engage the load generator, place switch SW2
in the ON position.
If the DAC code is changed from 01010 (1.300V), the
transient generator dynamics must be adjusted to the new
output voltage level. Place a scope probe in TP9 to measure
the voltage across the load resistors and the dv/dt across
them as well. Adjust the load resistors, R34-R38, to achieve
the correct load current level. Change resistors R30-R33 to
increase or decrease the dv/dt, as required, to match the
desired di/dt profile.
VCC12
Power Output Connections
The ISL6559EVAL2 output can be exercised using either
resistive or electronic loads. Copper alloy terminal lugs
provide connection points for loading. Tie the positive load
connection to VCORE, terminal J6, and the negative to
ground, terminal J7. A shielded scope probe test point, TP8,
allows for inspection of the output voltage, VCORE.
Enabling the Controller
The state of VCC, EN, and FS/DIS dictate the beginning of a
soft-start interval. The FS/DIS pin is only used to set the per
R28
46.4k ?
C61
1 μ F
HIP2100
HS
VSS
U5
R29
402 ?
M3
2N7002
HO
LO
C62
10 μ F
ON
OFF
SW2
phase switching frequency on the evaluation board. VCC is
tied to jumper JP1 which will arrive preset to +12V. Once the
input and output terminal connections are made, switch the
ENABLE switch (SW1) to the ON position. The EN signal is
released to rise above the ENABLE threshold of 1.23V
nominal. Once the ENABLE threshold is exceeded, a soft-
start interval is initiated. The output voltage will ramp in a
VCORE
D1
BAV99LT1
D2
R30
1.05k ?
R31
453 ?
R32
controlled manner with PGOOD changing from red to green
when the output voltage passes through the under-voltage
threshold.
Q7
HUF76129
Q8
HUF76129
BAV99LT1
1.05k ?
R33
453 ?
If JP1 is placed in the +5V position, the internal regulator of
the controller is disabled. The controller and drivers now are
R37
DNS
R35
0.100 ?
R34
0.500 ?
R36
0.200 ?
R38
DNS
TP9
VLOAD
enabled from two different sources. To prevent the controller
from enabling before the HIP660X drivers are active, the
threshold sensitive EN pin is used for power sequencing
between the controller and drivers. A resistor divider from
the +12V input is connected to EN. The resistors are
selected such that the ISL6559 enable threshold is reached
after the VCC rising threshold has been exceeded on all the
HIP6601 drivers.
FIGURE 1. LOAD TRANSIENT GENERATOR
ISL6559 VRD Performance
Soft-Start Interval
The typical start-up waveforms for the ISL6559EVAL2 are
shown in Figure 2. The DAC is set to 01010 (1.300V) and
the converter is started into a 52A load. The ENABLE switch,
SW1, is thrown to the ON position and the voltage on EN
2
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6560 WAF | 制造商:Intersil Corporation 功能描述: |
| ISL6560C WAF | 制造商:Intersil Corporation 功能描述: |
| ISL6560CB | 功能描述:IC REG CTRLR BUCK PWM CM 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6560CB-T | 功能描述:IC REG CTRLR BUCK PWM CM 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6560CBZ | 功能描述:IC REG CTRLR BUCK PWM CM 16-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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