参数资料
| 型号： | ISL6566IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 3PHASE 40-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL6566
Fault Monitoring and Protection
The ISL6566 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 13
outlines the interaction between the fault monitors and the
power good signal.
R OCSET
Undervoltage Detection
The undervoltage threshold is set at 82% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 85% of the VID code.
Overvoltage Protection
The ISL6566 constantly monitors the difference between the
VSEN and RGND voltages to detect if an overvoltage event
IREF
ISUM
+
ISEN
-
ICOMP
-
V DROOP
+
-
V OCSET
+
OCSET
100uA
occurs. During soft-start, while the DAC is ramping up, the
overvoltage trip level is the higher of DAC plus 150mV or a
fixed voltage, V OVP . The fixed voltage, V OVP , is 1.67V when
running in AMD Hammer, or VRM10 modes, and 1.97V for
VRM9 mode. Upon successful soft-start, the overvoltage trip
level is only DAC plus 150mV. OVP releases 50mV below its
trip point if it was “DAC plus 150mV” that tripped it, and
VDIFF
+1V
+
-
OC
releases 100mV below its trip point if it was the fixed voltage,
V OVP , that tripped it. Actions are taken by the ISL6566 to
protect the microprocessor load when an overvoltage
condition occurs, until the output voltage falls back within set
limits.
VID + 150mV
At the inception of an overvoltage event, all LGATE signals
are commanded high, and the PGOOD signal is driven low.
V OVP
SOFT-START, FAULT
AND CONTROL LOGIC
-
This causes the controller to turn on the lower MOSFETs
and pull the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high until
VDIFF falls to within the overvoltage limits explained above.
The ISL6566 will continue to protect the load in this fashion
as long as the overvoltage condition recurs.
VSEN
RGND
+
-
x1
+
-
+
OV
UV
PGOOD
Once an overvoltage condition ends the ISL6566 continues
normal operation and PGOOD returns high.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6566 is designed to protect the load from any overvoltage
events that may occur. This is accomplished by means of an
0.82 x DAC
ISL6566 INTERNAL CIRCUITRY
internal 10k ? resistor tied from PHASE to LGATE, which
turns on the lower MOSFET to control the output voltage
FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
ENLL, POR, or one of the no-CPU VID codes. If after an
undervoltage or overvoltage event occurs the output returns
to within under and overvoltage limits, PGOOD will return
high.
19
until the overvoltage event ceases or the input power supply
cuts off. For complete protection, the low side MOSFET
should have a gate threshold well below the maximum
voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6566 is designed to detect this
and shut down the controller. This event is detected by
monitoring the voltage on the IREF pin, which is a local
version of V OUT sensed at the outputs of the inductors.
FN9178.4
March 9, 2006
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| ISL6567CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6567CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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