参数资料
| 型号： | ISL6568CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 10/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM BUCK 2PHASE 32-QFN |
| 标准包装： | 1 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.84 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 标准包装 |
| 其它名称： | ISL6568CRZ-TDKR |
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ISL6568
( V IN – V OUT ) V OUT (EQ. 1)
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has a
combined ripple frequency three times greater than the ripple
frequency of any one phase. In addition, the peak-to-peak
amplitude of the combined inductor currents is reduced in
proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load current.
The ripple component has three times the ripple frequency of
each individual channel current. Each PWM pulse is terminated
1/3 of a cycle after the PWM pulse of the previous phase. The
peak-to-peak current for each phase is about 7A, and the DC
components of the inductor currents combine to feed the load.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.
I P-P = ------------------------------------------------------
L f S V IN
In Equation 1, V IN and V OUT are the input and output voltages
respectively, L is the single-channel inductor value, and f S is
the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 1 to the expression
for the peak-to-peak current after the summation of N
symmetrically phase-shifted inductor currents in Equation 2.
Peak-to-peak ripple current decreases by an amount
proportional to the number of channels. Output-voltage ripple
is a function of capacitance, capacitor equivalent series
resistance (ESR), and inductor ripple current. Reducing the
inductor ripple current allows the designer to use fewer or less
costly output capacitors.
12V to 1.5V at 36A. The single-phase converter has 11.9A RMS
input capacitor current. The single-phase converter must use an
input capacitor bank with twice the RMS current capacity as the
equivalent three-phase converter.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1 μ s/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR
RMS CURRENT FOR 3-PHASE CONVERTER
can be used to determine the input-capacitor RMS current
based on load current, duty cycle, and the number of channels.
They are provided as aids in determining the optimal input
capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of active
channels. The default channel setting for the ISL6568 is two.
One switching cycle is defined as the time between the
internal PWM1 pulse termination signals. The pulse
termination signal is the internally generated clock signal that
triggers the falling edge of PWM1. The cycle time of the pulse
termination signal is the inverse of the switching frequency set
by the resistor between the FS pin and ground. Each cycle
begins when the clock signal commands PWM1 to go low. The
PWM1 transition signals the internal channel-1 MOSFET driver
to turn off the channel-1 upper MOSFET and turn on the
channel-1 synchronous MOSFET. In the default channel
configuration, the PWM2 pulse terminates 1/2 of a cycle after
the PWM1 pulse.
If the BOOT2 and PHASE2 pins are both connected to +12V
I C ( P-P ) = ------------------------------------------------------------
( V IN – N V OUT ) V OUT
L f S V IN
(EQ. 2)
single channel operation is selected.
Once a PWM pulse transitions low, it is held low for a minimum
of 1/3 cycle. This forced off time is required to ensure an
Another benefit of interleaving is to reduce input ripple current.
Input capacitance is determined in part by the maximum input
ripple current. Multi-phase topologies can improve overall
system cost and size by lowering input ripple current and
allowing the designer to reduce the cost of input capacitance.
The example in Figure 2 illustrates input currents from a
three-phase converter combining to reduce the total input
ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
10
accurate current sample. Current sensing is described in the
next section. After the forced off time expires, the PWM output
is enabled. The PWM output state is driven by the position of
the error amplifier output signal, V COMP , minus the current
correction signal relative to the sawtooth ramp as illustrated in
Figure 3. When the modified V COMP voltage crosses the
sawtooth ramp, the PWM output transitions high. The internal
MOSFET driver detects the change in state of the PWM signal
and turns off the synchronous MOSFET and turns on the upper
MOSFET. The PWM signal will remain high until the pulse
termination signal marks the beginning of the next cycle by
triggering the PWM signal low.
FN9187.5
January 12, 2012
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