参数资料
| 型号： | ISL6568CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM BUCK 2PHASE 32-QFN |
| 标准包装： | 1 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.84 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 标准包装 |
| 其它名称： | ISL6568CRZ-TDKR |
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ISL6568
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to carry
about the same amount of current at any load level. To achieve
this, the currents through each channel must be sampled
every switching cycle. The sampled currents, I n , from each
active channel are summed together and divided by the
number of active channels. The resulting cycle average
current, I AVG , provides a measure of the total load-current
demand on the converter during each switching cycle.
period sample. The sampled current is used only for
channel-current balance.
I L
PWM
SWITCHING PERIOD
I SEN
SAMPLING PERIOD
Channel-current balance is achieved by comparing the
sampled current of each channel to the cycle average current,
OLD SAMPLE
CURRENT
NEW SAMPLE
CURRENT
and making the proper adjustment to each channel pulse
width based on the error. Intersil’s patented current-balance
method is illustrated in Figure 3, with error correction for
channel 1 represented. In the figure, the cycle average current,
I AVG , is compared with the channel 1 sample, I 1 , to create an
error signal I ER .
The filtered error signal modifies the pulse width commanded
by V COMP to correct any unbalance and force I ER toward zero.
The same method for error signal correction is applied to each
active channel.
TIME
FIGURE 4. SAMPLE AND HOLD TIMING
The ISL6568 supports MOSFET r DS(ON) current sensing to
sample each channel’s current for channel-current balance.
The internal circuitry, shown in Figure 5 represents channel n
of an N-channel converter. This circuitry is repeated for each
channel in the converter, but may not be active depending on
the status of the BOOT2 and PHASE2 pins, as described in
I SEN = I ------------------------- ) -
L R
V COMP
+
-
+
-
PWM1
TO GATE
CONTROL
LOGIC
I n
r DS ( ON
ISEN
V IN
CHANNEL N
UPPER MOSFET
f(s)
FILTER
Σ
R ISEN
SAWTOOTH SIGNAL
I ER
I AVG
÷ N
-
+
I 1
NOTE: Channel 2 is optional.
I 2
SAMPLE
&
HOLD
-
+
I L
ISEN(n)
-
I L r DS ( ON )
+
CHANNEL N
LOWER MOSFET
FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-BALANCE
ADJUSTMENT
ISL6565A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
Current Sampling
In order to realize proper current-balance, the currents in each
channel must be sampled every switching cycle. This sampling
occurs during the forced off-time, following a PWM transition
low. During this time the current-sense amplifier uses the ISEN
inputs to reproduce a signal proportional to the inductor
current, I L . This sensed current, I SEN , is simply a scaled version
of the inductor current. The sample window opens exactly 1/6
of the switching period, t SW , after the PWM transitions low.
The sample window then stays open the rest of the switching
cycle until PWM transitions high again, as illustrated in
Figure 4.
The sampled current, at the end of the t SAMPLE , is proportional
to the inductor current and is held until the next switching
11
FIGURE 5. ISL6568 INTERNAL AND EXTERNAL
CURRENT-SENSING CIRCUITRY FOR CURRENT
BALANCE
The ISL6568 senses the channel load current by sampling the
voltage across the lower MOSFET r DS(ON) , as shown in
Figure 5. A ground-referenced operational amplifier, internal to
the ISL6568, is connected to the PHASE node through a
resistor, R ISEN . The voltage across R ISEN is equivalent to the
voltage drop across the r DS(ON) of the lower MOSFET while it is
conducting. The resulting current into the ISEN pin is
proportional to the channel current, I L . The ISEN current is
FN9187.5
January 12, 2012
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