参数资料
型号: ISL6568CRZ-T
厂商: Intersil
文件页数: 15/30页
文件大小: 0K
描述: IC CTLR PWM BUCK 2PHASE 32-QFN
标准包装: 1
应用: 控制器,Intel VRM9,VRM10,AMD Hammer 应用
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.84 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 标准包装
其它名称: ISL6568CRZ-TDKR
ISL6568
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a
L
V L (s)
DCR
I OUT
precisely-controlled output impedance. This dependence of
output voltage on load current is often termed “droop” or “load
line” regulation.
PHASE1
R S
I
INDUCTOR
L 1
V OUT
C OUT
As shown in Figure 6, a voltage, V DROOP , proportional to the
total current in all active channels, I OUT , feeds into the
differential remote-sense amplifier. The resulting voltage at
the output of the remote-sense amplifier is the sum of the
output voltage and the droop voltage. Equation 4 shows that
PHASE2
R S
I
L
DCR
INDUCTOR
L 2
feeding this voltage into the compensation network causes the
regulator to adjust the output voltage so it will be equal to the
reference voltage minus the droop voltage.
ISUM
The droop voltage, V DROOP , is created by sensing the current
through the output inductors. This is accomplished by using a
continuous DCR current sensing method.
-
ICOMP
C COMP
R COMP
Inductor windings have a characteristic distributed resistance
or DCR (Direct Current Resistance). For simplicity, the inductor
V DROOP
+
IREF
(optional)
DCR is considered as a separate lumped quantity, as shown in
Figure 7. The channel current, I L , flowing through the inductor,
passes through the DCR. Equation 5 shows the s-domain
equivalent voltage, V L , across the inductor.
ISL6568
FIGURE 7. DCR SENSING CONFIGURATION
V L ( s ) = I L ? ( s ? L + DCR )
(EQ. 5)
By simply adjusting the value of R S , the load line can be set to
any level, giving the converter the right amount of droop at all
(EQ. 6)
? ------------- + 1 ?
? DCR ?
COMP
( s ? R
? C
+ 1 )
V ( s ) = -------------------------------------------------------------------------- ? ----------------------- ? ( I + I ) ? DCR
V DROOP = --------------------- ? I OUT ? DCR
The inductor DCR is important because the voltage dropped
across it is proportional to the channel current. By using a
simple R-C network and a current sense amplifier, as shown in
Figure 7, the voltage drop across all of the inductors’ DCRs can
be extracted. The output of the current sense amplifier,
V DROOP , can be shown to be proportional to the channel
currents I L1 and I L2 , shown in Equation 6.
s ? L
R
DROOP R L1 L2
COMP COMP S
If the R-C network components are selected such that the R-C
time constant matches the inductor L/DCR time constant,
then V DROOP is equal to the sum of the voltage drops across
the individual DCRs, multiplied by a gain. As Equation 7 shows,
V DROOP is therefore proportional to the total output current,
I OUT .
R COMP (EQ. 7)
R S
15
load currents. It may also be necessary to compensate for any
changes in DCR due to temperature. These changes cause the
load line to be skewed, and cause the R-C time constant to not
match the L/DCR time constant. If this becomes a problem a
simple negative temperature coefficient resistor network can
be used in the place of R COMP to compensate for the rise in
DCR due to temperature.
Note: An optional 10nF ceramic capacitor from the ISUM pin to
the IREF pin is recommended to help reduce any noise affects
on the current sense amplifier due to layout.
Output-Voltage Offset Programming
The ISL6568 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R OFS , from the OFS pin
to VCC or GND. When R OFS is connected between OFS and
VCC, the voltage across it is regulated to 1.5V. This causes a
proportional current (I OFS ) to flow into the OFS pin and out of
the FB pin. If R OFS is connected to ground, the voltage across it
is regulated to 0.5V, and I OFS flows into the FB pin and out of
the OFS pin. The offset current flowing through the resistor
between VDIFF and FB will generate the desired offset voltage
which is equal to the product (I OFS x R FB ). These functions are
shown in Figures 8 and 9.
FN9187.5
January 12, 2012
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