参数资料
型号: ISL6568IRZA
厂商: Intersil
文件页数: 17/30页
文件大小: 0K
描述: IC CTRLR PWM BUCK 2PHASE 32-QFN
标准包装: 60
应用: 控制器,Intel VRM9,VRM10,AMD Hammer 应用
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.84 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
ISL6568
accomplished by ensuring either rising gate turns on its MOSFET
with minimum and sufficient delay after the other has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released to
rise. An auto-zero comparator is used to correct the r DS(ON) drop
in the phase voltage preventing false detection of the -0.3V phase
level during r DS(ON) conduction period. In the case of zero current,
the UGATE is released after 35ns delay of the LGATE dropping
below 0.5V. During the phase detection, the disturbance of LGATE
falling transition on the PHASE node is blanked out to prevent
falsely tripping. Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE voltages
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Q GATE = 100nC
50nC
during a PWM falling edge and the subsequent UGATE turn-off. If
0.2
20nC
either the UGATE falls to less than 1.75V above the PHASE or the
PHASE falls to less than +0.8V, the LGATE is released to turn on.
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Internal Bootstrap Device
Both integrated drivers feature an internal bootstrap Schottky
diode. Simply adding an external capacitor across the BOOT
and PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
PHASE node. This reduces voltage stress on the boot to phase
pins.
The bootstrap capacitor must have a maximum voltage rating
above PVCC + 5V and its capacitance value can be chosen
from Equation 12:
Δ V BOOT_CAP (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
Gate Drive Voltage Versatility
The ISL6568 provides the user flexibility in choosing the gate
drive voltage for efficiency optimization. The controller ties the
upper and lower drive rails together. Simply applying a voltage
from 5V up to 12V on PVCC sets both gate drive rail voltages
simultaneously.
Initialization
C BOOT_CAP ≥ --------------------------------------
Q GATE
Δ V BOOT_CAP
(EQ. 12)
Prior to initialization, proper conditions must exist on the ENLL,
VCC, PVCC and the VID pins. When the conditions are met, the
controller begins soft-start. Once the output voltage is within the
proper window of operation, the controller asserts PGOOD.
Q GATE = ------------------------------------ ? N Q1
Q G1 ? PVCC
V GS1
where Q G1 is the amount of gate charge per upper MOSFET at
V GS1 gate-source voltage and N Q1 is the number of control
MOSFETs. The Δ V BOOT_CAP term is defined as the allowable
droop in the rail of the upper gate drive.
17
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state. This forces the drivers to short
gate-to-source of the upper and lower MOSFET’s to assure the
MOSFETs remain off. The following input conditions must be
met before the ISL6566 is released from this shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold
is reached, proper operation of all aspects of the ISL6568
is guaranteed. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6568 will not
inadvertently turn off unless the bias voltage drops
substantially (see “Electrical Specifications” on page 6).
FN9187.5
January 12, 2012
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