参数资料
型号: ISL6568IRZA
厂商: Intersil
文件页数: 26/30页
文件大小: 0K
描述: IC CTRLR PWM BUCK 2PHASE 32-QFN
标准包装: 60
应用: 控制器,Intel VRM9,VRM10,AMD Hammer 应用
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.84 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
ISL6568
0.6
0.4
When placing the MOSFETs try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally possible.
Input Bulk capacitors should be placed close to the drain of the
upper FETs and the source of the lower FETs. Locate the output
inductors and output capacitors between the MOSFETs and the load.
The high-frequency input and output decoupling capacitors
(ceramic) should be placed as close as practicable to the decoupling
target, making use of the shortest connection paths to any internal
planes, such as vias to GND next or on the capacitor solder pad.
0.2
I L(P-P) = 0
I L(P-P) = 0.5 I O
The critical small components include the bypass capacitors for
VCC and PVCC, and many of the components surrounding the
controller including the feedback network and current sense
components. Locate the VCC/PVCC bypass capacitors as close to
0
0
I L(P-P) = 0.75 I O
0.2 0.4
0.6
0.8
1.0
the ISL6566 as possible. It is especially important to locate the
components associated with the feedback circuit close to their
respective controller pins, since they belong to a high-impedance
DUTY CYCLE (V IN /V O )
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR
SINGLE-PHASE CONVERTER
Low capacitance, high-frequency ceramic capacitors are needed in
addition to the input bulk capacitors to suppress leading and
falling edge voltage spikes. The spikes result from the high current
slew rate produced by the upper MOSFET turn on and off. Select
low ESL ceramic capacitors and place one as close as possible to
each upper MOSFET drain to minimize board parasitics and
maximize suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which
the current transitions from one device to another causes voltage
spikes across the interconnecting impedances and parasitic
circuit elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit and lead to device overvoltage
stress. Careful component selection, layout, and placement
minimizes these voltage spikes. Consider, as an example, the
turnoff transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the turnoff,
current stops flowing in the upper MOSFET and is picked up by
the lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC converter
using a ISL6566 controller. The power components are the most
critical because they switch large amounts of energy. Next, are
small signal components that connect to sensitive nodes or
supply critical bypassing current and signal coupling.
The power components should be placed first, which include the
MOSFETs, input and output capacitors, and the inductors. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally across all
three power trains. Equidistant placement of the controller to the
three power trains also helps keep the gate drive traces equally
short, resulting in equal trace impedances and similar drive
capability of all sets of MOSFETs.
26
circuit loop, sensitive to EMI pick-up. It is also important to place
the current sense components close to their respective pins on
the ISL6566, including R ISEN , R S , R COMP , and C COMP .
A multi-layer printed circuit board is recommended. Figure 24 shows
the connections of the critical components for the converter. Note
that capacitors C xxIN and C xxOUT could each represent numerous
physical capacitors. Dedicate one solid layer, usually the one
underneath the component side of the board, for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels. Keep the
metal runs from the PHASE terminal to output inductors short. The
power plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom circuit
layers for the phase nodes. Use the remaining printed circuit layers
for small signal wiring.
Routing UGATE, LGATE, and PHASE Traces
Great attention should be paid to routing the UGATE, LGATE, and
PHASE traces since they drive the power train MOSFETs using
short, high current pulses. It is important to size them as large and
as short as possible to reduce their overall impedance and
inductance. They should be sized to carry at least one ampere of
current (0.02” to 0.05”). Going between layers with vias should also
be avoided, but if so, use two vias for interconnection when possible.
Extra care should be given to the LGATE traces in particular since
keeping their impedance and inductance low helps to significantly
reduce the possibility of shoot-through. It is also important to route
each channels UGATE and PHASE traces in as close proximity as
possible to reduce their inductances.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal GND
pad of the ISL6566 to the ground plane with multiple vias is
recommended. This heat spreading allows the part to achieve
its full thermal potential. It is also recommended that the
controller be placed in a direct path of airflow if possible to help
thermally manage the part.
FN9187.5
January 12, 2012
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