参数资料
型号: ISL6568IRZA
厂商: Intersil
文件页数: 21/30页
文件大小: 0K
描述: IC CTRLR PWM BUCK 2PHASE 32-QFN
标准包装: 60
应用: 控制器,Intel VRM9,VRM10,AMD Hammer 应用
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.84 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
ISL6568
At turn-on, the upper MOSFET begins to conduct and this
Calculating the power dissipation in the drivers for a desired
? I M I P-P ? ? ?
P UP ( 2 ) ≈ V IN ? ------ – ---------- ? ? ---- 2 ? f S
transition occurs over a time t 2 . In Equation 18, the
approximate power loss is P UP,2 .
t
? N 2 ? ? 2 ?
(EQ. 18)
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 5x5 QFN package is approximately 4W at
P UP ( 3 ) = V IN Q rr f S
A third component involves the lower MOSFET reverse-recovery
charge, Q rr . Since the inductor current has fully commutated to
the upper MOSFET before the lower-MOSFET body diode can
recover all of Q rr , it is conducted through the upper MOSFET
across VIN. The power dissipated as a result is P UP,3 .
(EQ. 19)
Finally, the resistive part of the upper MOSFET is given in
Equation 20 as P UP(4) .
room temperature. See “Layout Considerations” on page 26
for thermal transfer improvement suggestions.
When designing the ISL6568 into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P Qg_TOT , due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver
current can be estimated with Equations 21 and 22,
respectively.
I P-P2
? I M ?
P UP ( 4 ) ≈ r DS ( ON ) ? ------ ? d + ----------
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
2
(EQ. 20)
? N ? 12
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 17, 18, 19 and 20. Since the power equations
depend on MOSFET parameters, choosing the correct
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 21)
I DR = ? --- ? Q G1 ? N
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
3
? 2
Q1
(EQ. 22)
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of two drivers
in the controller package, the total power dissipated by both
drivers must be less than the maximum allowable power
dissipation for the QFN package.
In Equations 21 and 22, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power loss;
the gate charge (Q G1 and Q G2 ) is defined at the particular gate to
source drive voltage PVCC in the corresponding MOSFET data
sheet; I Q is the driver total quiescent current with no load at both
drive outputs; N Q1 and N Q2 are the number of upper and lower
MOSFETs per phase, respectively; N PHASE is the number of active
phases. The I Q* VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
PVCC
BOOT
C GD
D
R HI1
R LO1
UGATE
G
R G1
R GI1
C GS
C DS
Q1
S
PHASE
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
21
FN9187.5
January 12, 2012
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