参数资料
型号: ISL6610ACBZ-T
厂商: Intersil
文件页数: 9/11页
文件大小: 0K
描述: IC MOSFET DRVR DUAL SYNC 14-SOIC
标准包装: 2,500
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 18ns
配置数: 2
输出数: 4
高端电压 - 最大(自引导启动): 36V
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 带卷 (TR)
ISL6610, ISL6610A
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
– V
?
---------------------------------- ?
? dV ?
V GS_MILLER = ------- ? R ? C rss ? 1 – e dt
iss ?
------- ? R ? C
place a resistor (R UGPH ) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C GD /C GS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
dV
DS
dt ? ?
? ?
? ?
(EQ. 5)
C DS /C GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
R = R UGPH + R GI
C rss = C GD
C iss = C GD + C GS
the internal capacitive coupling. For most applications, the
integrated 20k Ω typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
following equations, which assume a fixed linear input ramp
and neglect the clamping effect of the body diode of the
VCC
BOOT
C BOOT
C GD
VIN
D
upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
DU
DL
UGATE
G
R GI
C DS
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10M Ω or greater) probe to
PHASE
C GS
S
Q UPPER
ensure a safe design margin.
FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
9
FN6395.0
November 22, 2006
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