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参数资料
| 型号： | ISL6615IBZ |
| 厂商： | Intersil |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC HF 6A 8-SOIC |
| 标准包装： | 980 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 10ns |
| 电流 - 峰： | 2.5A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 6.8 V ~ 13.2 V |
| 工作温度： | -40°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
ISL6615
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Tri-State Propagation Delay (Note 4)
SYMBOL
t PDHU
t PDHL
t PDLU
t PDLL
t PDTS
TEST CONDITIONS
V PVCC = 12V, 3nF Load, Adaptive
V PVCC = 12V, 3nF Load, Adaptive
V PVCC = 12V, 3nF Load
V PVCC = 12V, 3nF Load
V PVCC = 12V, 3nF Load
MIN
-
-
-
-
-
TYP
10
10
10
10
10
MAX
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
OUTPUT (Note 4 )
Upper Drive Source Current
Upper Drive Source Impedance
I U_SOURCE V PVCC = 12V, 3nF Load
R U_SOURCE 150mA Source Current
-
-
2.5
1
-
-
A
Ω
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
I U_SINK
R U_SINK
I L_SOURCE
V PVCC = 12V, 3nF Load
150mA Sink Current
V PVCC = 12V, 3nF Load
-
-
-
4
0.8
4
-
-
-
A
Ω
A
Lower Drive Source Impedance
R L_SOURCE 150mA Source Current
-
0.7
-
Ω
Lower Drive Sink Current
Lower Drive Sink Impedance
I L_SINK
R L_SINK
V PVCC = 12V, 3nF Load
150mA Sink Current
-
-
6
0.45
-
-
A
Ω
NOTE:
4. Limits established by characterization and are not production tested.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
1
2
DFN
1
2
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the “TIMING
DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.
-
3
3, 8
4
N/C
PWM
No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the “TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of
the controller.
4
5
6
7
5
6
7
9
GND
LGATE
VCC
PVCC
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN6481.0
April 24, 2008
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