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| 型号： | ISL6620IRZ |
| 厂商： | Intersil |
| 文件页数： | 5/10页 |
| 文件大小： | 0K |
| 描述： | IC SYNC RECT MOSFET DRVR 10-DFN |
| 标准包装： | 100 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 40ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 管件 |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
ISL6620, ISL6620A
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
Minimum Lgate on time at Diode emulation
SYMBOL
t_RL
t_FU
t_FL
t_PDHU
t_PDHL
t_PDLU
t_PDLL
t_LG_ON_DM
TEST CONDITIONS
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, adaptive
VCC = 5V, 3nF load, adaptive
VCC = 5V, 3nF load
VCC = 5V, 3nF load
VCC = 5V
MIN
230
TYP
8
8
4
40
23
18
25
330
MAX
450
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT (Note 4)
Upper Drive Source Current
I_U_Source
VCC = 5V, 3nF load
2
A
Upper Drive Source Impedance
R_U_SOURCE 20mA source current
1
Ω
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
I_U_SINK
R_U_SINK
I_L_SOURCE
VCC = 5V, 3nF load
20mA sink current
VCC = 5V, 3nF load
2
1
2
A
Ω
A
Lower Drive Source Impedance
R_L_SOURCE 20mA source current
1
Ω
Lower Drive Sink Current
Lower Drive Sink Impedance
I_L_SINK
R_L_SINK
VCC = 5V, 3nF load
20mA sink current
4
0.4
A
Ω
NOTE:
4. Limits should be considered typical and are not production tested.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
1
2
DFN
1
2
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
-
3
3, 8
4
NC
PWM
No connect.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation.
See “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output
of the controller.
4
5
6
5
6
7
GND
LGATE
VCC
Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to 5V bias supply. This pin supplies power to the upper gate and lower gate drive. Place a high
quality low ESR ceramic capacitor from this pin to GND.
7
8
9
10
EN
PHASE
Enable input pin. Connect this pin high to enable driver and low to disable driver.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
-
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN6494.0
April 25, 2008
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