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参数资料
| 型号： | ISL6622IBZ |
| 厂商： | Intersil |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC BUCK 8-SOIC |
| 标准包装： | 980 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 20ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 6.8 V ~ 13.2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
ISL6622
Pre-POR Overvoltage Protection
While VCC is below its POR level, the upper gate is held low
and LGATE is connected to the PHASE pin via an internal
10k Ω (typically) resistor. By connecting the PHASE node to
the gate of the low side MOSFET, the driver offers some
passive protection to the load if the upper MOSFET(s) is or
becomes shorted. If the PHASE node goes higher than the
gate threshold of the lower MOSFET, it results in the
progressive turn-on of the device and the effective clamping
of the PHASE node’s rise. The actual PHASE node clamping
.
1.6
1.4
1.2
1.0
0.8
0.6
level depends on the lower MOSFET’s electrical
characteristics, as well as the characteristics of the input
supply and the path connecting it to the respective PHASE
node.
0.4
0.2
20nC
Q UGATE = 100nC
50nC
Internal Bootstrap Device
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
The ISL6622 features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces the voltage
stress on the BOOT to PHASE pins.
The bootstrap capacitor must have a maximum voltage
rating well above the maximum voltage intended for UVCC.
Its minimum capacitance value can be estimated from
Equation 1:
Δ V BOOT_CAP (V)
FIGURE 5. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F SW ), the output drive impedance, the
layout resistance, and the selected MOSFET’s internal gate
resistance and total gate charge (Q G ). Calculating the power
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
C BOOT_CAP ≥ --------------------------------------
Q UGATE = ------------------------------------ ? N Q1
Q UGATE
Δ V BOOT_CAP
Q G1 ? UVCC
V GS1
(EQ. 1)
recommended operating junction temperature. The DFN
package is more suitable for high frequency applications. See
“ Layout Considerations ” on page 9 for thermal impedance
improvement suggestions. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated using Equations 2 and 3, respectively:
P Qg_Q1 = --------------------------------------- ? F SW ? N Q1
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The Δ V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 5.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
Q G1 ? UVCC 2
V GS1
(EQ. 2)
P Qg_Q2 = -------------------------------------- ? F SW ? N Q2
? Q G1 ? UVCC ? N Q1 Q G2 ? LVCC ? N Q2 ?
I DR = ? ? ? F SW + I Q
Q G2 ? LVCC 2
V GS2
------------------------------------------------------ + -----------------------------------------------------
? V GS1 V GS2 ?
(EQ. 3)
where the gate charge (Q G1 and Q G2 ) is defined at a
particular gate to source voltage (V GS1 and V GS2 ) in the
corresponding MOSFET datasheet; I Q is the driver ’s total
quiescent current with no load at both drive outputs; N Q1
and N Q2 are number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I Q* VCC
product is the quiescent power of the driver without a load.
8
FN6470.2
October 30, 2008
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