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| 型号： | ISL6622IBZ |
| 厂商： | Intersil |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC BUCK 8-SOIC |
| 标准包装： | 980 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 20ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 6.8 V ~ 13.2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
ISL6622
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (R G1 and R G2 ) and the internal gate
resistors (R GI1 and R GI2 ) of MOSFETs. Figures 6 and 7 show
the typical upper and lower gate drives turn-on current paths.
help minimize such unwanted stress. The following advice is
meant to lead to an optimized layout:
? Keep decoupling loops (LVCC-GND and BOOT-PHASE)
as short as possible.
? Minimize trace inductance, especially low-impedance
lines: all power traces (UGATE, PHASE, LGATE, GND,
LVCC) should be short and wide, as much as possible.
P DR = P DR_UP + P DR_LOW + I Q ? VCC
(EQ. 4)
? Minimize the inductance of the PHASE node: ideally, the
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
2
2
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
? Minimize the input current loop: connect the source of the
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source
R EXT1 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
R GI1
Q1
R GI2
Q2
of lower MOSFETs as possible.
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
.
UVCC
BOOT
C GD
D
copper area can be extended beyond the bottom area of the
IC and/or connected to buried power ground plane(s) with
thermal vias. This combination of vias for vertical heat
escape, extended surface copper islands, and buried planes
R HI1
R LO1
G
R L1
R G1
C GS
C DS
Q1
combine to allow the IC and the power switches to achieve
their full thermal potential.
Upper MOSFET Self Turn-On Effect at Start-up
S
PHASE
FIGURE 6. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC
D
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to
self-coupling via the internal C GD of the MOSFET, the gate
of the upper MOSFET could momentarily rise up to a level
greater than the threshold voltage of the device, potentially
turning on the upper switch. Therefore, if such a situation
R HI2
R LO2
G
R L2
C GD
R G2
C GS
C DS
Q2
could conceivably be encountered, it is a common practice
to place a resistor (R UGPH ) across the gate and source of
the upper MOSFET to suppress the Miller coupling effect.
The value of the resistor depends mainly on the input
voltage’s rate of rise, the C GD /C GS ratio, as well as the gate-
source threshold of the upper MOSFET. A higher dV/dt, a
S
FIGURE 7. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
lower C DS /C GS ratio, and a lower gate-source threshold
upper FET will require a smaller resistor to diminish the
effect of the internal capacitive coupling. For most
applications, the integrated 20k Ω resistor is sufficient, not
affecting normal performance and efficiency.
– V
?
---------------------------------- ?
? dV ?
V GS_MILLER = ------- ? R ? C rss ? 1 – e dt
iss ?
------ ? R ? C
Layout Considerations
During switching of the devices, the parasitic inductances of
the PCB and the power devices’ packaging (both upper and
lower MOSFETs) leads to ringing, possibly in excess of the
dV
DS
dt ? ?
? ?
? ?
(EQ. 5)
absolute maximum rating of the devices. Careful layout can
R = R UGPH + R GI
C rss = C GD
C iss = C GD + C GS
The coupling effect can be roughly estimated with
Equation 5, which assumes a fixed linear input ramp and
neglects the clamping effect of the body diode of the upper
drive and the bootstrap capacitor. Other parasitic
9
FN6470.2
October 30, 2008
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