参数资料
| 型号： | ISL6627IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/11页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER VR11.1 VR12 10DFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VR11.1，VR12 |
| 输出数： | 1 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 带卷 (TR) |
ISL6627
PWM
t PDHU
t PDLU
1.6V<PWM<3.2V
t PDTS
1.1V<PWM<2.8V
t UG_OFF_DB
t PDTS
UGATE
LGATE
t FL
t RU
t FU
t PDHL
t RL
t PDLL
t PDLFUR
t TSSHD
t PDUFLR
FIGURE 2. TIMING DIAGRAM
Operation and Adaptive Shoot-Through
Protection
Designed for high speed switching, the ISL6627 MOSFET driver
controls both high-side and low-side N-Channel FETs from one
externally-provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see “Timing Diagram”). After a short propagation delay
[t PDLL ], the lower gate begins to fall. Typical fall times [t FL ] are
provided in the “ Electrical Specifications” on page 4. Adaptive
shoot-through circuitry monitors the LGATE voltage and turns on
the upper gate following a short delay time [t PDHU ] after the LGATE
voltage drops below ~1V. The user also has the option to program
the propagation delay as described in “Deadtime Programming”
upper MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short propagation
delay [t PDLU ] is encountered before the upper gate begins to fall
[t FU ]. The adaptive shoot-through circuitry monitors the UGATE-
PHASE voltage and turns on the lower MOSFET a short delay time
[t PDHL ], after the upper MOSFET’s gate voltage drops below 1V.
The lower gate then rises [t RL ], turning on the lower MOSFET.
These methods prevent both the lower and upper MOSFETs from
conducting simultaneously (shoot-through), while adapting the
dead time to the gate charge characteristics of the MOSFETs being
used. The user also has the option to program the propagation
This driver is optimized for voltage regulators with a large step
down ratio. The lower MOSFET is usually sized larger compared to
the upper MOSFET because the lower MOSFET conducts for a
longer time during a switching period. The lower gate driver is
therefore sized much larger to meet this application requirement.
The 0.4 Ω ON-resistance and 4A sink current capability enable the
lower gate driver to absorb the charge injected into the lower gate
through the drain-to-gate capacitor of the lower MOSFET and help
prevent shoot through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
6
Advanced PWM Protocol (Patent Pending)
The advanced PWM protocol of ISL6627 is specifically designed
to work with Intersil VR11.1 and VR12 controllers. When
ISL6627 detects a PSI# protocol sent by an Intersil
VR11.1/VR12 controller, it turns on diode emulation operation;
otherwise, it remains in normal CCM PWM mode.
Note that for a PWM low to tri-level (2.5V) transition, the LGATE
will not turn off until the its diode emulation minimum ON-time
of 330ns (typically) passes.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the ISL6627
detects the zero current crossing of the output inductor and turns
off LGATE, preventing the low side MOSFET from sinking current
and ensuring discontinuous conduction mode (DCM) is achieved.
In DCM mode, LGATE has a minimum ON-time of 330ns
(typically).
Deadtime Programming
The part provides the user with the option to program either of the
two gate propagation delays (as defined in Figure 3) in order to
optimize the deadtime and maximize the efficiency of the circuit.
Tying the TD pin to either GND or VCC through a specified-value
resistor leads the driver to operate in fixed gate propagation delay
mode. Leaving the TD pin floating results in the driver operating
in adaptive deadtime mode. Refer to Table 1 for typical
programming resistor value options. Propagation delay has a
typical tolerance of 30%. As actual deadtime depends on FET
switching transition characteristics, while operating in fixed
propagation delay mode, the user needs to monitor the gate
transitions under worst-case operating conditions and use
appropriate design margin to prevent eventual shoot-through due
to insufficient dead time.
FN6992.1
January 24, 2014
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