参数资料
| 型号： | ISL6627IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER VR11.1 VR12 10DFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VR11.1，VR12 |
| 输出数： | 1 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 带卷 (TR) |
ISL6627
PWM
LG
UG
LG FALL TO UG RISE PROPAGATION DELAY
UG FALL TO LG RISE PROPAGATION DELAY
where Q G1 is the amount of gate charge per upper MOSFET at
V GS1 gate-source voltage and N Q1 is the number of control
(upper) MOSFETs. The Δ V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive. Select results
are exemplified in Figure 4.
1.6
1.4
1.2
1.
0.8
FIGURE 3. PROGRAMMABLE PROPAGATION DELAY
ILLUSTRATION
TABLE 1. TYPICAL DELAY PROGRAMMING RESISTOR VALUE
0.6
0.4
Q GATE = 100nC
50nC
RESISTOR FROM RESISTOR FROM
LG FALL TO
UG FALL TO
0.2
20nC
TD TO VCC
(k ? )
TD TO GND
(k ? )
UG RISE DELAY
(ns)
LG RISE DELAY
(ns)
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
short
100
330
910
-
-
-
Floating
-
-
-
-
Short
100
360
Floating
27
27
27
27
40
25
17
Adaptive
23
18
15
7
18
18
18
Adaptive
Δ V BOOT_CAP (V)
FIGURE 4. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency (F SW ), the output drive impedance, the layout
resistance, the selected MOSFET’s internal gate resistance and its
total gate charge (Q G ). Calculating the power dissipation in the
driver for a desired application is critical to ensure safe operation.
Exceeding the maximum allowable power dissipation level may
push the IC beyond the maximum recommended operating
Q G1 ? UVCC 2
P Qg_Q1 = ----------------------------------- ? F SW ? N Q1
Q G2 ? LVCC 2
P Qg_Q2 = ---------------------------------- ? F SW ? N Q2
Power-On Reset (POR) Function
VCC voltage level is monitored at all times. Once the VCC voltage
exceeds 3.85V (typically), operation of the driver is enabled and
the PWM input signal takes control of the gate drivers. If VCC
drops below the falling threshold of 3.52V (typically), operation of
the driver is disabled.
Internal Bootstrap Device
ISL6627 features an internal bootstrap schottky diode. Simply
adding an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit. The bootstrap function is also
designed to prevent the bootstrap capacitor from overcharging
due to the large negative swing at the trailing-edge of the PHASE
junction temperature. The DFN package is more suitable for high
frequency applications. See “Layout Considerations” on page 8 for
thermal impedance improvement suggestions. The total driver
power loss, essentially MOSFETs’ gate charge and driver internal
circuitry losses, can be estimated using Equations 2 and 3,
respectively.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
V GS1 (EQ. 2)
V GS2
I DR = ? ------------------------------------------------ + ------------------------------------------------ ? ? F SW + I Q
node excursion. This reduces the potential for overstressing the
upper driver.
The bootstrap capacitor must have a voltage rating above the
? Q G1 ? UVCC ? N Q1 Q G2 ? LVCC ? N Q2 ?
? V GS1 V GS2 ?
(EQ. 3)
C BOOT_CAP ≥ ---------------------------------
Q G1 ? VCC
Q GATE = --------------------------- ? N Q1
maximum VCC voltage. Its capacitance value can be estimated
from Equation 1:
Q GATE
Δ V BOOT_CAP
(EQ. 1)
V GS1
7
where the gate charge (Q G1 and Q G2 ) is defined at a particular
gate to source voltage (V GS1 and V GS2 ) in the corresponding
MOSFET datasheet; I Q is the driver’s total quiescent current with
no load at both drive outputs; N Q1 and N Q2 are number of upper
and lower MOSFETs, respectively; UVCC and LVCC are the drive
voltages for both upper and lower FETs, respectively. The I Q* VCC
product is the bias power of the driver without a load.
FN6992.1
January 24, 2014
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